1
2
Assuntos:
“...Technology mapping...”
Graph based algorithms to efficiently map VLSI circuits with simple cells
Tese
3
Assuntos:
“...CMOS technology...”
Aging aware design techniques and CMOS gate degradation estimative
Tese
4
Assuntos:
“...Technology mapping...”
Exploração de reordenamento de ROBDDs no mapeamento tecnológico de circuitos integrados
Dissertação
5
Assuntos:
“...Technology mapping...”
Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools
Dissertação
6
Assuntos:
“...Technology mapping...”
Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition
Dissertação
7
Assuntos:
“...Technology mapping...”
Automatic generation and evaluation of transistor networks in different logic styles
Tese
8
Assuntos:
“...Library-free technology mapping...”
On-silicon testbench for validation of soft logic cell libraries
Dissertação
9
Assuntos:
“...Nanometer technology...”
SAT based environment for logical capacity evaluation of via configurable block templates
Tese
10
Assuntos:
“...Technology mapping...”
KL-cuts : a new approach for logic synthesis targeting multiple output blocks
Dissertação
11
Assuntos:
“...Technology mapping...”
Technology mapping for virtual libraries based on cells with minimal transistor stacks
Tese