An aI based tool for networks-on-chip design space exploration

• Ano de defesa: 2018
• Autor(a) principal: Silva, Jefferson Igor Duarte
• Orientador(a): Kreutz, Márcio Eduardo
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Programa de Pós-Graduação: PROGRAMA DE PÓS-GRADUAÇÃO EM SISTEMAS E COMPUTAÇÃO
• País: Brasil
• Palavras-chave em Português: Network-on-chip; Artificial intelligence; Design space exploration
• Área do conhecimento CNPq: CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO
• Link de acesso: https://repositorio.ufrn.br/jspui/handle/123456789/25937

With the increasing number of cores in Systems on Chip (SoCs), bus architectures have suffered some limitations regarding performance. As applications demand more bandwidth and lower latencies, busses could not comply with such requirements due to longer wires and increased capacitancies. Facing this scenario, Networks-on-Chip (NoCs) emerged as a way to overcome limitations found in bus-based systems. NoCs are composed of a set of routers and communication links. Each component has its own characteristics. Fully exploring all possible NoC characteristics settings is unfeasible due to the huge design space to cover. Therefore, some methods to speed up this process are needed. In this work, we propose the usage of Artificial Intelligence techniques to optimize NoC architectures. This is accomplished by developing an AI based tool to explore the design space in terms of area, latency, and power prediction for different NoCs components configuration. Up to now, nine classifiers were evaluated. To evaluate this tool, tests were performed on Audio/Video applications with Bit-Reversal, Butterfly, Uniform, Perfect Shuffle, and Transpose Matrix traffic patterns, with four different communication requirements. The first result show an accuracy up to 88% and to 100%, using Decision Trees to predict latency and area/power values, respectively. As second step, a Genetic Algorithm was applied to explore the design space and the reached results ratify that the solutions found are valid and adequate to the constraints of the designer.