Controladores discretos de tensão baseados no princípio do modelo interno aplicados a inversores trifásicos PWM - Botterón, Fernando (2005)
This thesis contributes to the analysis, project and implementation of discrete-time controllers based on the Internal Model Principle, aiming to improve the performance of three-leg three-phase PWM inverters with insulating output transformer usually found in the output stage of medium power double-conversion UPS. Initially, an investigation about issues concerning to the discrete-time models of three-phase inverters with space vector modulation and the LC filter have been carried out. This investigation shows the impact of different switching sequences, sampling instants and filter cut-off frequency on the harmonic spectrum of sampled variables used for feedback. This is a concern when the switching frequency is low to limit the switching losses as in medium and high power UPS. In this way, this thesis proposes sampling methods that make possible to reduce the low order harmonics on the interest variables, which is relevant when state feedback is used. These methods allow to obtain discrete-time average linear models useful for the controller design. In addition, the saturation of the insulating transformer is addressed in details. The dc component arising from the digital implementation and from the circuit measures non idealities, and then amplified by an inadequate choice of the controller, may lead the transformer to saturate. In order to solve this problem, and in accordance with the Internal Model Principle, internal models adequate to the plant under consideration as well as discrete-time voltage controllers in stationary and synchronous frames which are not prone to amplify the dc component, are proposed. Another goal of this thesis is the improvement of the UPS output voltage transient response due to linear and non linear load steps. This is obtained considering the sampling methods before mentioned, combined with internal models with reduced number of poles and low sampling rate. It is demonstrated that it is possible to improve significantly the output voltage transient responses, as well as to satisfy the rigorous classification of the standard IEC62040-3 for UPS without degrading the steady state performance. In addition, these control structures have enough stability margins, as proved in each case, and they results in simple and attractive solutions to be implemented in 8 or 16 bits fixed-point arithmetic microcontrollers and DSP with reduced memory space. The feasibility of the proposed solutions is verified with experimental results demonstrating both transient and steady-state performances. Finally, a comparative analysis of the proposed control structures, over the light of the standard IEC62040-3, is presented.