An application specific signal processor for gaseous detector systems in high energy physics experiment. - Sanches, Bruno Cavalcante de Souza (2021)
In this thesis, a study on front-ends for high energy physics was developed focusing on the ALICE experiment upgrade at the CERN LHC. Due to a higher event rate and several other changes, the development of a new ASIC was necessary to support the signal readout in the TPC and MCH detectors. This chip was named SAMPA (Serialized Analog-digital Multi-Purpose ASIC) and is a continuous readout mixed-signal integrated circuit with 32 channels. The present work fundamentally addresses the digital part of this chip and the improvements, methodologies and strategies used in its development. The previous ASIC used in TPC presented erroneous lockout events in its FIR filters and aiming in a solution for this, the signal conditioning and baseline correction filters were modified concerning also their fault tolerance and resistance to errors caused by radiation. A new non-linear filter complementary to the existing filters was implemented so that an uninterrupted baseline tracking ability could be achieved. A dedicated packet-based protocol with error correction capabilities is also proposed, tolerating up to two faults per header and adding just 0.07% bandwidth overhead. To achieve the final solution for CERN, four different prototypes were manufactured using TSMC 130 nm technology, which were SAMPA MPW1, V2, V3 and V4. These versions were necessary to incrementally achieve an optimal design satisfying the several constraints and specifications required. The initial implementation was a reduced version with 3 channels, that was further irradiated with protons being the initial source of cross-section data for SAMPA. With these practical results, the first complete version of the chip was designed, the SAMPA V2, being a unique ASIC never realized before. This chip was functionally tested and was very close to the CERNs needs. However, irradiations revealed problems related to latch-ups. A latch-up prevention technique was further developed during this thesis, which was applied to the new versions of the chip. A novel optimization system based on genetic algorithms was also proposed to obtain balanced implementations concerning area, power and error tolerance. Two more versions, SAMPA V3 and V4, were developed implementing corrections and improvements in the radiation tolerance of the digital part. New irradiations showed that the design was adequate and a pulsed laser test confirmed the hypotheses raised about the origin of the latch-ups, wherewith the proposed changes, a reduction of more than 99% of the cross-section was achieved. Finally, with the successful measurements, SAMPA V4 was approved for use by the ALICE collaboration. An additional prototype named SAMPA MPW5 was further designed, permitting the extension of this work by performing tests with the optimizer and new implementations of the FIR baseline correction filter and the SAR ADC control block. The designs were tested and validated through irradiations using the Pelletron accelerator at USP; with these measurements, new mean times between failures were obtained showing improvements greater than a thousand times and also providing a relevant architectural and experimental base for new projects.