Analysis of voltage scaling effects in the design of resilient circuits
Ano de defesa: | 2016 |
---|---|
Autor(a) principal: | |
Orientador(a): | |
Banca de defesa: | |
Tipo de documento: | Dissertação |
Tipo de acesso: | Acesso aberto |
Idioma: | eng |
Instituição de defesa: |
Pontif?cia Universidade Cat?lica do Rio Grande do Sul
|
Programa de Pós-Graduação: |
Programa de P?s-Gradua??o em Ci?ncia da Computa??o
|
Departamento: |
Faculdade de Inform?tica
|
País: |
Brasil
|
Palavras-chave em Português: | |
Área do conhecimento CNPq: | |
Link de acesso: | http://tede2.pucrs.br/tede2/handle/tede/6615 |
Resumo: | Although the advancement of semiconductor technology enable the fabrication of devices with increasingly reduced propagation delay, potentially leading to higher operating frequencies, manufacturing process variability grows very aggressively in modern processes. To cope with growing variability phenomena, significant delay margins need to be added to clock signal?s periods, to ensure timing closure, which limits performance gains and constrains power efficiency. Among the several techniques that have been explored in the last decades to address these problems, three are quite relevant and promising either in isolation or combined: voltage scaling, asynchronous circuits and resilient architectures. This work investigates how voltage scaling affects circuit path delays, and produces three sets of original contributions. The first set establishes a technique to ensure that circuits synthesized with a reduced library achieve results comparable to the full library, while keeping functionality at low supply voltages. The second set of contributions composes a method to extend the voltage corners supported by standard cell libraries. This takes place through new library characterization techniques. The third set of contributions provides insights on the effects of voltage scaling in the design of resilient circuits. This analysis evaluates supply voltages in super- and sub-threshold levels. |
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Calazans, Ney Laert Vilar265.426.840-34http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4781414E5009.333.190-88http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4332578J3Gibiluka, Matheus2016-04-19T18:32:43Z2016-03-04http://tede2.pucrs.br/tede2/handle/tede/6615Although the advancement of semiconductor technology enable the fabrication of devices with increasingly reduced propagation delay, potentially leading to higher operating frequencies, manufacturing process variability grows very aggressively in modern processes. To cope with growing variability phenomena, significant delay margins need to be added to clock signal?s periods, to ensure timing closure, which limits performance gains and constrains power efficiency. Among the several techniques that have been explored in the last decades to address these problems, three are quite relevant and promising either in isolation or combined: voltage scaling, asynchronous circuits and resilient architectures. This work investigates how voltage scaling affects circuit path delays, and produces three sets of original contributions. The first set establishes a technique to ensure that circuits synthesized with a reduced library achieve results comparable to the full library, while keeping functionality at low supply voltages. The second set of contributions composes a method to extend the voltage corners supported by standard cell libraries. This takes place through new library characterization techniques. The third set of contributions provides insights on the effects of voltage scaling in the design of resilient circuits. This analysis evaluates supply voltages in super- and sub-threshold levels.Embora o avan?o da tecnologia de semicondutores permita a fabrica??o de dispositivos com atrasos de propaga??o reduzidos, potencialmente habilitando o aumento da frequ?ncia de opera??o, as varia??es em processos de fabrica??o modernos crescem de forma muito agressiva. Para lidar com este problema, significativas margens de atraso devem ser adicionadas ao per?odo de sinais de rel?gio, limitando os ganhos em desempenho e a efici?ncia energ?tica do circuito. Entre as diversas t?cnicas exploradas nas ?ltimas d?cadas para amenizar esta dificuldade, tr?s se destacam como relevantes e promissoras, isoladas ou combinadas: a redu??o da tens?o de alimenta??o, o uso de projeto ass?ncrono e arquiteturas resilientes. Este trabalho investiga como a redu??o de tens?o de alimenta??o afeta os atrasos de caminhos em circuitos digitais, e produz tr?s contribui??es originais. A primeira ? a defini??o uma t?cnica para garantir que circuitos sintetizados com um conjunto reduzido de c?lulas atinjam resultados comparaveis aos da biblioteca completa, mantendo a sua funcionalidade mesmo quando alimentados por tens?es reduzidas. A segunda ? a composi??o de um m?todo para estender o suporte a n?veis de tens?o de alimenta??o para bibliotecas de c?lulas padr?o providas por fabicantes de CIs, atrav?s de novas t?cnicas de caracteriza??o de bibliotecas. A terceira ? a an?lise dos efeitos do escalamento de tens?o no projeto de circuitos resilientes, considerando tens?es de alimenta??o superiores e inferiores ? tens?o de limiar dos transistores.Submitted by Setor de Tratamento da Informa??o - BC/PUCRS (tede2@pucrs.br) on 2016-04-19T18:32:43Z No. of bitstreams: 1 DIS_MATHEUS_GIBILUKA_COMPLETO.pdf: 3498426 bytes, checksum: 534aec97d6aa9dfc7b535a7f65087ae1 (MD5)Made available in DSpace on 2016-04-19T18:32:43Z (GMT). No. of bitstreams: 1 DIS_MATHEUS_GIBILUKA_COMPLETO.pdf: 3498426 bytes, checksum: 534aec97d6aa9dfc7b535a7f65087ae1 (MD5) Previous issue date: 2016-03-04application/pdfhttp://tede2.pucrs.br:80/tede2/retrieve/164603/DIS_MATHEUS_GIBILUKA_COMPLETO.pdf.jpgengPontif?cia Universidade Cat?lica do Rio Grande do SulPrograma de P?s-Gradua??o em Ci?ncia da Computa??oPUCRSBrasilFaculdade de Inform?ticaCIRCUITOS ASS?NCRONOSCIRCUITOS DIGITAISINFORM?TICACIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAOAnalysis of voltage scaling effects in the design of resilient circuitsAn?lise dos efeitos de escalamento de tens?o no projeto de circuitos resilientesinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesis1974996533081274470600600600-30085425104011491443671711205811204509info:eu-repo/semantics/openAccessreponame:Biblioteca Digital de Teses e Dissertações da PUC_RSinstname:Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)instacron:PUC_RSTHUMBNAILDIS_MATHEUS_GIBILUKA_COMPLETO.pdf.jpgDIS_MATHEUS_GIBILUKA_COMPLETO.pdf.jpgimage/jpeg3589http://tede2.pucrs.br/tede2/bitstream/tede/6615/4/DIS_MATHEUS_GIBILUKA_COMPLETO.pdf.jpg95a649d9490655a8f49b1750fd7af88dMD54TEXTDIS_MATHEUS_GIBILUKA_COMPLETO.pdf.txtDIS_MATHEUS_GIBILUKA_COMPLETO.pdf.txttext/plain224503http://tede2.pucrs.br/tede2/bitstream/tede/6615/3/DIS_MATHEUS_GIBILUKA_COMPLETO.pdf.txt10ef187dd376530354b75cd81ace528dMD53ORIGINALDIS_MATHEUS_GIBILUKA_COMPLETO.pdfDIS_MATHEUS_GIBILUKA_COMPLETO.pdfapplication/pdf3498426http://tede2.pucrs.br/tede2/bitstream/tede/6615/2/DIS_MATHEUS_GIBILUKA_COMPLETO.pdf534aec97d6aa9dfc7b535a7f65087ae1MD52LICENSElicense.txtlicense.txttext/plain; charset=utf-8610http://tede2.pucrs.br/tede2/bitstream/tede/6615/1/license.txt5a9d6006225b368ef605ba16b4f6d1beMD51tede/66152016-04-19 20:00:51.087oai:tede2.pucrs.br:tede/6615QXV0b3JpemHDp8OjbyBwYXJhIFB1YmxpY2HDp8OjbyBFbGV0csO0bmljYTogQ29tIGJhc2Ugbm8gZGlzcG9zdG8gbmEgTGVpIEZlZGVyYWwgbsK6OS42MTAsIGRlIDE5IGRlIGZldmVyZWlybyBkZSAxOTk4LCBvIGF1dG9yIEFVVE9SSVpBIGEgcHVibGljYcOnw6NvIGVsZXRyw7RuaWNhIGRhIHByZXNlbnRlIG9icmEgbm8gYWNlcnZvIGRhIEJpYmxpb3RlY2EgRGlnaXRhbCBkYSBQb250aWbDrWNpYSBVbml2ZXJzaWRhZGUgQ2F0w7NsaWNhIGRvIFJpbyBHcmFuZGUgZG8gU3VsLCBzZWRpYWRhIGEgQXYuIElwaXJhbmdhIDY2ODEsIFBvcnRvIEFsZWdyZSwgUmlvIEdyYW5kZSBkbyBTdWwsIGNvbSByZWdpc3RybyBkZSBDTlBKIDg4NjMwNDEzMDAwMi04MSBiZW0gY29tbyBlbSBvdXRyYXMgYmlibGlvdGVjYXMgZGlnaXRhaXMsIG5hY2lvbmFpcyBlIGludGVybmFjaW9uYWlzLCBjb25zw7NyY2lvcyBlIHJlZGVzIMOgcyBxdWFpcyBhIGJpYmxpb3RlY2EgZGEgUFVDUlMgcG9zc2EgYSB2aXIgcGFydGljaXBhciwgc2VtIMO0bnVzIGFsdXNpdm8gYW9zIGRpcmVpdG9zIGF1dG9yYWlzLCBhIHTDrXR1bG8gZGUgZGl2dWxnYcOnw6NvIGRhIHByb2R1w6fDo28gY2llbnTDrWZpY2EuCg==Biblioteca Digital de Teses e Dissertaçõeshttp://tede2.pucrs.br/tede2/PRIhttps://tede2.pucrs.br/oai/requestbiblioteca.central@pucrs.br||opendoar:2016-04-19T23:00:51Biblioteca Digital de Teses e Dissertações da PUC_RS - Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)false |
dc.title.por.fl_str_mv |
Analysis of voltage scaling effects in the design of resilient circuits |
dc.title.alternative.por.fl_str_mv |
An?lise dos efeitos de escalamento de tens?o no projeto de circuitos resilientes |
title |
Analysis of voltage scaling effects in the design of resilient circuits |
spellingShingle |
Analysis of voltage scaling effects in the design of resilient circuits Gibiluka, Matheus CIRCUITOS ASS?NCRONOS CIRCUITOS DIGITAIS INFORM?TICA CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
title_short |
Analysis of voltage scaling effects in the design of resilient circuits |
title_full |
Analysis of voltage scaling effects in the design of resilient circuits |
title_fullStr |
Analysis of voltage scaling effects in the design of resilient circuits |
title_full_unstemmed |
Analysis of voltage scaling effects in the design of resilient circuits |
title_sort |
Analysis of voltage scaling effects in the design of resilient circuits |
author |
Gibiluka, Matheus |
author_facet |
Gibiluka, Matheus |
author_role |
author |
dc.contributor.advisor1.fl_str_mv |
Calazans, Ney Laert Vilar |
dc.contributor.advisor1ID.fl_str_mv |
265.426.840-34 |
dc.contributor.advisor1Lattes.fl_str_mv |
http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4781414E5 |
dc.contributor.authorID.fl_str_mv |
009.333.190-88 |
dc.contributor.authorLattes.fl_str_mv |
http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4332578J3 |
dc.contributor.author.fl_str_mv |
Gibiluka, Matheus |
contributor_str_mv |
Calazans, Ney Laert Vilar |
dc.subject.por.fl_str_mv |
CIRCUITOS ASS?NCRONOS CIRCUITOS DIGITAIS INFORM?TICA |
topic |
CIRCUITOS ASS?NCRONOS CIRCUITOS DIGITAIS INFORM?TICA CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
dc.subject.cnpq.fl_str_mv |
CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
description |
Although the advancement of semiconductor technology enable the fabrication of devices with increasingly reduced propagation delay, potentially leading to higher operating frequencies, manufacturing process variability grows very aggressively in modern processes. To cope with growing variability phenomena, significant delay margins need to be added to clock signal?s periods, to ensure timing closure, which limits performance gains and constrains power efficiency. Among the several techniques that have been explored in the last decades to address these problems, three are quite relevant and promising either in isolation or combined: voltage scaling, asynchronous circuits and resilient architectures. This work investigates how voltage scaling affects circuit path delays, and produces three sets of original contributions. The first set establishes a technique to ensure that circuits synthesized with a reduced library achieve results comparable to the full library, while keeping functionality at low supply voltages. The second set of contributions composes a method to extend the voltage corners supported by standard cell libraries. This takes place through new library characterization techniques. The third set of contributions provides insights on the effects of voltage scaling in the design of resilient circuits. This analysis evaluates supply voltages in super- and sub-threshold levels. |
publishDate |
2016 |
dc.date.accessioned.fl_str_mv |
2016-04-19T18:32:43Z |
dc.date.issued.fl_str_mv |
2016-03-04 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/masterThesis |
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masterThesis |
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publishedVersion |
dc.identifier.uri.fl_str_mv |
http://tede2.pucrs.br/tede2/handle/tede/6615 |
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http://tede2.pucrs.br/tede2/handle/tede/6615 |
dc.language.iso.fl_str_mv |
eng |
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eng |
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1974996533081274470 |
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600 600 600 |
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3671711205811204509 |
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openAccess |
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Pontif?cia Universidade Cat?lica do Rio Grande do Sul |
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Programa de P?s-Gradua??o em Ci?ncia da Computa??o |
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PUCRS |
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Pontif?cia Universidade Cat?lica do Rio Grande do Sul |
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