Algoritmo de Posicionamento Polinomial para FPGA Baseado em Travessia de Grafos

• Ano de defesa: 2013
• Autor(a) principal: Cardoso, Luciana Rocha
• Orientador(a): Ferreira, Ricardo dos Santos
• Banca de defesa: Nacif, José Augusto Miranda
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Viçosa
• Programa de Pós-Graduação: Mestrado em Ciência da Computação
• Departamento: Metodologias e técnicas da Computação; Sistemas de Computação
• País: BR
• Palavras-chave em Português: FPGA; Posicionamento; Tempo de execução
• Palavras-chave em Inglês: FPGA; Positioning; Execution time
• Área do conhecimento CNPq: CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://locus.ufv.br/handle/123456789/2662

Nowadays, many applications requires high performance solutions, which could not be achieved by a software approach. Problems in bioinformatics, simulations, telecommunications, encryption, compression of large volumes of data are examples of these applications. A hardware approaches are high-performance, however, these approaches have high design costs. The reconfigurable hardware is an intermediate solution between software and hardware, as it offers the flexibility of the software and the performance of the hardware. Since 1980s, FPGA circuits have emerged as commercial and scalable platform for reconfigurable hardware. Several problems have been modeled and implemented by using FPGA with acceleration from 2 to 3 orders of magnitude. However, the FPGA complexity has significantly increased from hundreds of logical blocks/interconnections to the order of millions in last decades. First, the application should be mapped to the FPGA. The mapping consists on two steps: placement and routing. The placement will map the computing elements in logic blocks. This step is NP-Complete. Then, the routing step will perform the interconnections between the logic blocks. It is also a NP-complete problem. Both problems are one of current challenges in FPGA tools. Several heuristics have been proposed, but few of them are suitable for run-time approach. This dissertation proposes an exploration of the design space of a polynomial algorithm based on graph traversal. Depth-first and Breadth-first traversals are evaluated by looking the reconvergent fanout and high fanout nodes. Experimental results analyze the execution time, critical path, distribution degree and total wire length.