Adequa??o de modelos arquiteturais para aplica??es tempo-real em sistemas many-core
Ano de defesa: | 2017 |
---|---|
Autor(a) principal: | |
Orientador(a): | |
Banca de defesa: | |
Tipo de documento: | Tese |
Tipo de acesso: | Acesso aberto |
Idioma: | por |
Instituição de defesa: |
Pontif?cia Universidade Cat?lica do Rio Grande do Sul
|
Programa de Pós-Graduação: |
Programa de P?s-Gradua??o em Ci?ncia da Computa??o
|
Departamento: |
Faculdade de Inform?tica
|
País: |
Brasil
|
Palavras-chave em Português: | |
Área do conhecimento CNPq: | |
Link de acesso: | http://tede2.pucrs.br/tede2/handle/tede/7360 |
Resumo: | The evolution of integrated circuit manufacturing process allowed the SoC (System-on- Chip) design in the 90?s, and currently the design of multiprocessors systems on chip ? MPSoCs (Multiprocessor System-on-Chip). Embedded systems use these devices, due to the offered computational power. The MPSoC design is a challenging task. Specify the MPSoC characteristics, define the components that compose the system and analyze their features are decisions that may change over the product development. Traditional design methods do not favor the design space exploration, leading to expensive products due to required hardware simulation at the gate level, which is only available at the end of the design flow. To solve the design problems of traditional methods, Platform Based Design (PBD) techniques is a design choice. The basis of PBD is a virtual platform model, enabling fast simulations, software debugging and reusability of hardware components. This Thesis comprises the study and development in two research axes: (1) modeling of virtual platforms; (2) analytical methods for software heuristics targeting embedded real-time applications. Virtual platforms are modeled by using ADLs (Architecture Description Languages). This work presents the modeling of several virtual platforms, using different abstraction levels (from RTL to untimed models) and memory architectures (shared and distributed). Based on the evaluations performed in each architecture, the HeMPS platform was adapted to execute real-time applications. The results showed that using the proposed scheduling mechanism and RTA mapping, the results meet the constraints defined by the applications. Comparing platforms with mapping and schedule heuristics on literature, the proposed platform met 100% of the restrictions resulting from the test cases. |
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Moraes, Fernando Gehm477.763.820-00http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4782943Z2018.526.750-55http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4475017P0Madalozzo, Guilherme Afonso2017-06-23T14:59:40Z2017-01-12http://tede2.pucrs.br/tede2/handle/tede/7360The evolution of integrated circuit manufacturing process allowed the SoC (System-on- Chip) design in the 90?s, and currently the design of multiprocessors systems on chip ? MPSoCs (Multiprocessor System-on-Chip). Embedded systems use these devices, due to the offered computational power. The MPSoC design is a challenging task. Specify the MPSoC characteristics, define the components that compose the system and analyze their features are decisions that may change over the product development. Traditional design methods do not favor the design space exploration, leading to expensive products due to required hardware simulation at the gate level, which is only available at the end of the design flow. To solve the design problems of traditional methods, Platform Based Design (PBD) techniques is a design choice. The basis of PBD is a virtual platform model, enabling fast simulations, software debugging and reusability of hardware components. This Thesis comprises the study and development in two research axes: (1) modeling of virtual platforms; (2) analytical methods for software heuristics targeting embedded real-time applications. Virtual platforms are modeled by using ADLs (Architecture Description Languages). This work presents the modeling of several virtual platforms, using different abstraction levels (from RTL to untimed models) and memory architectures (shared and distributed). Based on the evaluations performed in each architecture, the HeMPS platform was adapted to execute real-time applications. The results showed that using the proposed scheduling mechanism and RTA mapping, the results meet the constraints defined by the applications. Comparing platforms with mapping and schedule heuristics on literature, the proposed platform met 100% of the restrictions resulting from the test cases.A evolu??o no processo de fabrica??o de circuitos integrados permitiu o projeto de SoCs na d?cada de 1990, e atualmente o projeto de sistemas multiprocessados em um ?nico chip - MPSoCs (Multiprocessor System-on-Chip). Estes dispositivos s?o amplamente utilizados em sistemas embarcados, dado o poder computacional oferecido pelos mesmos. Aplica??es com restri??es de tempo-real v?m sendo utilizadas constantemente, sendo um desafio para o projeto de SoCs. O projeto de MPSoCs ? altamente complexo. Especificar as caracter?sticas do MPSoC, definir os componentes que comp?e o sistema e analisar suas funcionalidades s?o decis?es que podem apresentar altera??es ao longo do desenvolvimento do produto. M?todos tradicionais de projeto n?o favorecem as tomadas de decis?es e encarecem o produto, pois requerem simula??o em n?vel de hardware, estando dispon?vel apenas no final do fluxo de projeto. Para solucionar os problemas apresentados pelos m?todos tradicionais de projeto, adotou-se a t?cnica de projeto baseado em plataforma (PBD ? Platform Based Design). O m?todo de projeto PBD adota a modelagem de plataformas virtuais em n?vel de sistema possibilitando r?pidas simula??es, depura??o de software e reuso de componentes de hardware. Esta Tese tem por objetivo realizar estudos e desenvolvimentos em 2 eixos de pesquisa: (1) modelagem de plataformas virtuais com diferentes organiza??es de mem?ria; (2) estudo de m?todos anal?ticos para mecanismos de software em sistemas com restri??es de tempo-real. Para a modelagem de plataformas virtuais usa-se as ADLs (Architecture Description Language) OVP e ArchC. Neste tema de trabalho, diversas plataformas foram modeladas em diferentes n?veis de abstra??o (de RTL a modelos sem temporiza??o) e com diferentes arquiteturas de mem?ria (compartilhada e distribu?da). Com base nas avalia??es realizadas em cada arquitetura, adequou-se a plataforma HeMPS para executar aplica??es com restri??es de tempo-real. Os resultados apresentaram que, com a utiliza??o do mecanismo de escalonamento e do mapeamento RTA propostos, os dados resultantes das aplica??es com restri??es de tempo-real aconteceram dentro do per?odo de tempo definido pela aplica??o. Comparando plataformas com heur?sticas de mapeamento e escalonamento presentes na literatura, a plataforma desenvolvida na presente Tese atende as restri??es de aplica??es Hard-RT, garantindo 100% das restri??es resultantes dos casos de testes.Submitted by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-06-23T14:59:40Z No. of bitstreams: 1 TES_GUILHERME_AFONSO_MADALOZZO_COMPLETO.pdf: 2690462 bytes, checksum: f0014136baae215c473fedda8527433f (MD5)Made available in DSpace on 2017-06-23T14:59:40Z (GMT). No. of bitstreams: 1 TES_GUILHERME_AFONSO_MADALOZZO_COMPLETO.pdf: 2690462 bytes, checksum: f0014136baae215c473fedda8527433f (MD5) Previous issue date: 2017-01-12Funda??o de Amparo ? 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dc.title.por.fl_str_mv |
Adequa??o de modelos arquiteturais para aplica??es tempo-real em sistemas many-core |
dc.title.alternative.eng.fl_str_mv |
Adaption of architetural models for real-time applications in many-core systems |
title |
Adequa??o de modelos arquiteturais para aplica??es tempo-real em sistemas many-core |
spellingShingle |
Adequa??o de modelos arquiteturais para aplica??es tempo-real em sistemas many-core Madalozzo, Guilherme Afonso Sistemas Many-core Modelagem de Sistemas Many-core Aplica??es Tempo-real Escalonamento Mapeamento CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
title_short |
Adequa??o de modelos arquiteturais para aplica??es tempo-real em sistemas many-core |
title_full |
Adequa??o de modelos arquiteturais para aplica??es tempo-real em sistemas many-core |
title_fullStr |
Adequa??o de modelos arquiteturais para aplica??es tempo-real em sistemas many-core |
title_full_unstemmed |
Adequa??o de modelos arquiteturais para aplica??es tempo-real em sistemas many-core |
title_sort |
Adequa??o de modelos arquiteturais para aplica??es tempo-real em sistemas many-core |
author |
Madalozzo, Guilherme Afonso |
author_facet |
Madalozzo, Guilherme Afonso |
author_role |
author |
dc.contributor.advisor1.fl_str_mv |
Moraes, Fernando Gehm |
dc.contributor.advisor1ID.fl_str_mv |
477.763.820-00 |
dc.contributor.advisor1Lattes.fl_str_mv |
http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4782943Z2 |
dc.contributor.authorID.fl_str_mv |
018.526.750-55 |
dc.contributor.authorLattes.fl_str_mv |
http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4475017P0 |
dc.contributor.author.fl_str_mv |
Madalozzo, Guilherme Afonso |
contributor_str_mv |
Moraes, Fernando Gehm |
dc.subject.por.fl_str_mv |
Sistemas Many-core Modelagem de Sistemas Many-core Aplica??es Tempo-real Escalonamento Mapeamento |
topic |
Sistemas Many-core Modelagem de Sistemas Many-core Aplica??es Tempo-real Escalonamento Mapeamento CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
dc.subject.cnpq.fl_str_mv |
CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
description |
The evolution of integrated circuit manufacturing process allowed the SoC (System-on- Chip) design in the 90?s, and currently the design of multiprocessors systems on chip ? MPSoCs (Multiprocessor System-on-Chip). Embedded systems use these devices, due to the offered computational power. The MPSoC design is a challenging task. Specify the MPSoC characteristics, define the components that compose the system and analyze their features are decisions that may change over the product development. Traditional design methods do not favor the design space exploration, leading to expensive products due to required hardware simulation at the gate level, which is only available at the end of the design flow. To solve the design problems of traditional methods, Platform Based Design (PBD) techniques is a design choice. The basis of PBD is a virtual platform model, enabling fast simulations, software debugging and reusability of hardware components. This Thesis comprises the study and development in two research axes: (1) modeling of virtual platforms; (2) analytical methods for software heuristics targeting embedded real-time applications. Virtual platforms are modeled by using ADLs (Architecture Description Languages). This work presents the modeling of several virtual platforms, using different abstraction levels (from RTL to untimed models) and memory architectures (shared and distributed). Based on the evaluations performed in each architecture, the HeMPS platform was adapted to execute real-time applications. The results showed that using the proposed scheduling mechanism and RTA mapping, the results meet the constraints defined by the applications. Comparing platforms with mapping and schedule heuristics on literature, the proposed platform met 100% of the restrictions resulting from the test cases. |
publishDate |
2017 |
dc.date.accessioned.fl_str_mv |
2017-06-23T14:59:40Z |
dc.date.issued.fl_str_mv |
2017-01-12 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/doctoralThesis |
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doctoralThesis |
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publishedVersion |
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http://tede2.pucrs.br/tede2/handle/tede/7360 |
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http://tede2.pucrs.br/tede2/handle/tede/7360 |
dc.language.iso.fl_str_mv |
por |
language |
por |
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1974996533081274470 |
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600 600 600 600 |
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-3008542510401149144 |
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3671711205811204509 |
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info:eu-repo/semantics/openAccess |
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openAccess |
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Pontif?cia Universidade Cat?lica do Rio Grande do Sul |
dc.publisher.program.fl_str_mv |
Programa de P?s-Gradua??o em Ci?ncia da Computa??o |
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PUCRS |
dc.publisher.country.fl_str_mv |
Brasil |
dc.publisher.department.fl_str_mv |
Faculdade de Inform?tica |
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Pontif?cia Universidade Cat?lica do Rio Grande do Sul |
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