T?cnicas de toler?ncia a falhas aplicadas a redes intra-chip
Ano de defesa: | 2015 |
---|---|
Autor(a) principal: | |
Orientador(a): | |
Banca de defesa: | |
Tipo de documento: | Dissertação |
Tipo de acesso: | Acesso aberto |
Idioma: | por |
Instituição de defesa: |
Pontif?cia Universidade Cat?lica do Rio Grande do Sul
|
Programa de Pós-Graduação: |
Programa de P?s-Gradua??o em Ci?ncia da Computa??o
|
Departamento: |
Faculdade de Inform?tica
|
País: |
Brasil
|
Palavras-chave em Português: | |
Área do conhecimento CNPq: | |
Link de acesso: | http://tede2.pucrs.br/tede2/handle/tede/6140 |
Resumo: | The continuous development of the transistor technology has enabled hundreds of processors to work interconnected by a NoC (network-on-chip). Nanotechnology has enabled the development of complex systems, however, fault vulnerability also increased. The literature presents partial solutions for fault tolerance issues, targeting parts of the system. An important gap in the literature is an integrated method from the router-level fault detection to the correct execution of applications in the MPSoC. The main goal of this dissertation is to present a fault-tolerant method from the physical layer to the transport layer. The MPSoC is modeled at the RTL level using VHDL.This work proposes fault tolerance techniques applied to intra-chip networks. Related work on fault tolerance at a systemic level, router level, link level and routing algorithms are studied. This work presents the research and development of two techniques: (i) protocols to enable the correct communication between task with partial degradation of the link enabling the router to operate even with faulted physical channels; (ii) test recovery method and of the router. This Dissertation considers permanent and transient faults.The HeMPS platform is the reference platform to evaluate the proposed techniques, together with a fault injection campaign where up to five random failures were injected simultaneously at each simulated scenario. Two applications were used to evaluate the proposed techniques, MPEG encoder and a synthetic application, resulting in 2,000 simulated scenarios. The results demonstrated the effectiveness of the proposal, with most scenarios running correctly with routers operating in degraded mode, with an impact on the execution time below 1%, with a router area overhead around 30%. |
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Moraes, Fernando Gehm477.763.820-00011.038.840-26http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4292929A6Fochi, Vinicius Morais2015-06-16T17:21:57Z2015-03-13http://tede2.pucrs.br/tede2/handle/tede/6140The continuous development of the transistor technology has enabled hundreds of processors to work interconnected by a NoC (network-on-chip). Nanotechnology has enabled the development of complex systems, however, fault vulnerability also increased. The literature presents partial solutions for fault tolerance issues, targeting parts of the system. An important gap in the literature is an integrated method from the router-level fault detection to the correct execution of applications in the MPSoC. The main goal of this dissertation is to present a fault-tolerant method from the physical layer to the transport layer. The MPSoC is modeled at the RTL level using VHDL.This work proposes fault tolerance techniques applied to intra-chip networks. Related work on fault tolerance at a systemic level, router level, link level and routing algorithms are studied. This work presents the research and development of two techniques: (i) protocols to enable the correct communication between task with partial degradation of the link enabling the router to operate even with faulted physical channels; (ii) test recovery method and of the router. This Dissertation considers permanent and transient faults.The HeMPS platform is the reference platform to evaluate the proposed techniques, together with a fault injection campaign where up to five random failures were injected simultaneously at each simulated scenario. Two applications were used to evaluate the proposed techniques, MPEG encoder and a synthetic application, resulting in 2,000 simulated scenarios. The results demonstrated the effectiveness of the proposal, with most scenarios running correctly with routers operating in degraded mode, with an impact on the execution time below 1%, with a router area overhead around 30%.O cont?nuo desenvolvimento na tecnologia de transistores possibilitou que centenas de processadores trabalhassem interconectados por NoCs (network-on-chip). A nanotecnologia permitiu o desenvolvimento de complexos sistemas, por?m a vulnerabilidade a falhas tamb?m aumentou. A literatura apresenta solu??es parciais para o tema de toler?ncia a falhas, tendo como alvo partes do sistema. Uma importante lacuna na literatura ? um m?todo integrado para detec??o de falhas do n?vel do roteador at? a correta execu??o das aplica??es em MPSoC reais. O objetivo principal desta disserta??o ? apresentar um m?todo com toler?ncia a falhas da camada f?sica at? a camada de transporte. O MPSoC ? modelado em n?vel de RTL, usando VHDL.O presente trabalho prop?e t?cnicas de toler?ncia a falhas aplicadas a redes intrachip. S?o estudadas t?cnicas de toler?ncia a falhas em n?vel sist?mico, n?vel do roteador, n?vel de enlace e algoritmos de roteamento tolerante a falhas. Este trabalho apresenta a pesquisa e o desenvolvimento de duas t?cnicas: (i) protocolos para permitir a correta transmiss?o dos dados com degrada??o parcial do enlace, de forma a permitir que o roteador opere mesmo com canais f?sicos falhos; (ii) m?todo de teste e recupera??o do roteador. O modelo de falhas utilizado nesta Disserta??o ? de falhas permanentes e transientes.Para avaliar as t?cnicas propostas, foi utilizada a plataforma HeMPS, juntamente com uma campanha de inje??o de falhas onde at? cinco falhas aleat?rias foram injetadas nos canais de comunica??o entre os roteadores simultaneamente em cada cen?rio. Foram utilizadas duas aplica??es para avaliar as t?cnicas: codificador MPEG e uma aplica??o sint?tica, com um total de 2,000 cen?rios simulados. Os resultados demonstram a efetividade da proposta, com a maioria dos cen?rios executando corretamente com roteadores operando em modo degradado, com um impacto no tempo de execu??o abaixo de 1% e um aumente do ?rea de 30% no roteador.Submitted by Setor de Tratamento da Informa??o - BC/PUCRS (tede2@pucrs.br) on 2015-06-16T17:21:57Z No. of bitstreams: 1 470587 - Texto Completo.pdf: 6163395 bytes, checksum: b88f0389d39c7cc7f197b32966e6fe29 (MD5)Made available in DSpace on 2015-06-16T17:21:57Z (GMT). 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dc.title.por.fl_str_mv |
T?cnicas de toler?ncia a falhas aplicadas a redes intra-chip |
title |
T?cnicas de toler?ncia a falhas aplicadas a redes intra-chip |
spellingShingle |
T?cnicas de toler?ncia a falhas aplicadas a redes intra-chip Fochi, Vinicius Morais INFORM?TICA ARQUITETURA DE COMPUTADOR TOLER?NCIA A FALHAS (INFORM?TICA) MULTIPROCESSADORES CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
title_short |
T?cnicas de toler?ncia a falhas aplicadas a redes intra-chip |
title_full |
T?cnicas de toler?ncia a falhas aplicadas a redes intra-chip |
title_fullStr |
T?cnicas de toler?ncia a falhas aplicadas a redes intra-chip |
title_full_unstemmed |
T?cnicas de toler?ncia a falhas aplicadas a redes intra-chip |
title_sort |
T?cnicas de toler?ncia a falhas aplicadas a redes intra-chip |
author |
Fochi, Vinicius Morais |
author_facet |
Fochi, Vinicius Morais |
author_role |
author |
dc.contributor.advisor1.fl_str_mv |
Moraes, Fernando Gehm |
dc.contributor.advisor1ID.fl_str_mv |
477.763.820-00 |
dc.contributor.authorID.fl_str_mv |
011.038.840-26 |
dc.contributor.authorLattes.fl_str_mv |
http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4292929A6 |
dc.contributor.author.fl_str_mv |
Fochi, Vinicius Morais |
contributor_str_mv |
Moraes, Fernando Gehm |
dc.subject.por.fl_str_mv |
INFORM?TICA ARQUITETURA DE COMPUTADOR TOLER?NCIA A FALHAS (INFORM?TICA) MULTIPROCESSADORES |
topic |
INFORM?TICA ARQUITETURA DE COMPUTADOR TOLER?NCIA A FALHAS (INFORM?TICA) MULTIPROCESSADORES CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
dc.subject.cnpq.fl_str_mv |
CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
description |
The continuous development of the transistor technology has enabled hundreds of processors to work interconnected by a NoC (network-on-chip). Nanotechnology has enabled the development of complex systems, however, fault vulnerability also increased. The literature presents partial solutions for fault tolerance issues, targeting parts of the system. An important gap in the literature is an integrated method from the router-level fault detection to the correct execution of applications in the MPSoC. The main goal of this dissertation is to present a fault-tolerant method from the physical layer to the transport layer. The MPSoC is modeled at the RTL level using VHDL.This work proposes fault tolerance techniques applied to intra-chip networks. Related work on fault tolerance at a systemic level, router level, link level and routing algorithms are studied. This work presents the research and development of two techniques: (i) protocols to enable the correct communication between task with partial degradation of the link enabling the router to operate even with faulted physical channels; (ii) test recovery method and of the router. This Dissertation considers permanent and transient faults.The HeMPS platform is the reference platform to evaluate the proposed techniques, together with a fault injection campaign where up to five random failures were injected simultaneously at each simulated scenario. Two applications were used to evaluate the proposed techniques, MPEG encoder and a synthetic application, resulting in 2,000 simulated scenarios. The results demonstrated the effectiveness of the proposal, with most scenarios running correctly with routers operating in degraded mode, with an impact on the execution time below 1%, with a router area overhead around 30%. |
publishDate |
2015 |
dc.date.accessioned.fl_str_mv |
2015-06-16T17:21:57Z |
dc.date.issued.fl_str_mv |
2015-03-13 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
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info:eu-repo/semantics/masterThesis |
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masterThesis |
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http://tede2.pucrs.br/tede2/handle/tede/6140 |
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http://tede2.pucrs.br/tede2/handle/tede/6140 |
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por |
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1974996533081274470 |
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600 600 600 |
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Pontif?cia Universidade Cat?lica do Rio Grande do Sul |
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Programa de P?s-Gradua??o em Ci?ncia da Computa??o |
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Brasil |
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Faculdade de Inform?tica |
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Pontif?cia Universidade Cat?lica do Rio Grande do Sul |
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