Development of an intellectual-property core to detect task scheduling errors in rtos-based embedded systems

• Ano de defesa: 2021
• Autor(a) principal: Fracalossi, Aline Schröpfer
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul; Escola Politécnica; Brasil; PUCRS; Programa de Pós-Graduação em Engenharia Elétrica
• Palavras-chave em Português: Task Scheduler; Real-Time Operating System (RTOS); Embedded System for Critical Application; Multicore Processor; Fault-Tolerance; Escalonamento de Tarefas; Sistemas Operacional de Tempo Real (RTOS); Sistemas Embarcados para Aplicações Críticas; Processador Multicore; Tolerância a Falhas; ENGENHARIAS
• Link de acesso: http://tede2.pucrs.br/tede2/handle/tede/10051

The employment of a Real-Time Operating System (RTOS) has become an attractive solution for designing critical real-time embedded systems that are part of our daily lives. For these systems, the correct functioning depends not only on the correct logical response, but also on the time at which the answer is given. In this regard, RTOS has emerged as an interesting solution for multiple processing cores. Furthermore, the market pressures to reduce the energy consumption that these multicore embedded systems need to operate. The main consequence of this pressure is the higher susceptibility to transient failures. This type of failure can affect the task scheduling process and change the system correct functioning. In this scenario, it is necessary to have a solution to improve the reliability of the scheduling process. Therefore, this dissertation develops and validates an Intellectual-Property Core (I-IP) able to monitor the Earliest Deadline First (EDF) scheduling algorithm running on a single core system. The I-IP performs passive monitoring of the system’s task scheduling to detect failures. Described in Very-High-Speed Integrated Circuits Hardware Description Language (VHDL), the I-IP is connected to the processor address bus to perform system monitoring. The proposed technique was implemented in the HF-RISC softcore processor (namely Hellfire processor), which was running under the control of the HF-RISC Operating System (HellfireOS). Simulation results indicate that the proposed technique effectively detects faults that induce task scheduling malfunctioning at runtime, while incurring acceptable penalties, of low area overhead and negligible energy consumption increase.