A framework for fast architecture exploration of convolutional neural network accelerators

• Ano de defesa: 2022
• Autor(a) principal: Juracy, Leonardo Rezende
• Tipo de documento: Tese
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul; Escola Politécnica; Brasil; PUCRS; Programa de Pós-Graduação em Ciência da Computação
• Palavras-chave em Português: Redes Neurais Convolucionais; Acelerador de Hardware de Convolução; Simulador de Sistema; PPA; Exploração do Espaço de Projeto; Convolutional Neural Networks; Convolution Hardware Accelerator; System Simulator; Design Space Exploration; CIENCIA DA COMPUTACAO::TEORIA DA COMPUTACAO
• Link de acesso: https://tede2.pucrs.br/tede2/handle/tede/10437

Machine Learning (ML) is a sub-area of artificial intelligence comprehending algorithms to solve classification and pattern recognition problems. One of the most common ways to deliver ML nowadays is using Artificial Neural Networks, specifically Convolutional Neural Networks (CNN). GPUs became the reference platforms for both training and inference phases of CNNs due to their tailored architecture to the CNN operators. However, GPUs are powerhungry architectures. A path to enable the deployment of CNNs in energy-constrained devices is by adopting hardware accelerators for the inference phase. However, the literature presents gaps regarding analyses and comparisons of these accelerators to evaluate Power-Performance-Area (PPA) trade-offs. Typically, the literature estimates PPA from the number of executed operations during the inference phase, such as the number of Multiplier-Accumulators (MAC), which may not reflect the actual hardware behavior. Thus, it is necessary to deliver accurate hardware estimations, enabling design space exploration (DSE) to deploy CNNs according to the design constraints. This Thesis proposes two DSE approaches for CNNs. The former adopts a cycle-accurate system simulator and uses a highlevel language to describe the hardware abstractly. This first approach uses TensorFlow as a front-end for training, while the back-end generates performance estimations through physical synthesis of hardware accelerators. The second approach is a fast and accurate DSE, using an analytical model fitted from the physical synthesis of hardware accelerators. The analytic model estimates area, performance, power, energy, and memory accesses. The observed worst-case average error comparing the analytical model to the data obtained from the physical synthesis is smaller than 8%. Although the second approach generate accurate results in a fast way, the first approach enables simulating a complete computational system, considering a possible accelerators modeling redundancy. This Thesis advances the state-of-the-art by offering methods to generate a comprehensive PPA evaluation, integrating front-end frameworks (e.g., TensorFlow) to a back-end design flow.