Hardware-based approach to support mixed-critical workload execution in multicore processors

• Ano de defesa: 2015
• Autor(a) principal: Green, Bruno Naspolini
• Orientador(a): Vargas, Fabian Luis
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Pontif?cia Universidade Cat?lica do Rio Grande do Sul
• Programa de Pós-Graduação: Programa de P?s-Gradua??o em Engenharia El?trica
• Departamento: Faculdade de Engenharia
• País: Brasil
• Palavras-chave em Português: MULTIPROCESSADORES; PROCESSAMENTO DE ALTO DESEMPENHO; INFORM?TICA
• Área do conhecimento CNPq: ENGENHARIAS
• Link de acesso: http://tede2.pucrs.br/tede2/handle/tede/6641

The use of multicore processors in general-purpose real-time embedded systems has experienced a huge increase in the recent years. Unfortunately, critical applications are not benefiting from this type of processors as one could expect. The major obstacle is that we may not predict and provide any guarantee on real-time properties of software running on such platforms. The shared memory bus is among the most critical resources, which severely degrades the timing predictability of multicore software due to the access contention between cores. To counteract this problem, we present in this work a new approach that supports mixed-criticality workload execution in a multicore processor-based embedded system. It allows any number of cores to run less-critical tasks concurrently with the critical core, which is running the critical task. The approach is based on the use of a dedicated Hard Deadline Enforcer (HDE) implemented in hardware, which allows the execution of any number of cores (running less-critical workloads) concurrently with the critical core (executing the critical workload). From the best of our knowledge, compared to existing techniques, the proposed approach allows the exploitation of the maximum performance offered by a multiprocessing system while guaranteeing critical task schedulability. Additionally, the proposed approach presents the same design complexity as any other approach devoted to perform timing analysis for single core processor, no matter the number of cores are used in the embedded system on the design. If current techniques were used, the design complexity to perform timing analysis would increase dramatically as long as the number of cores in the embedded system increases. A case-study based on a dual-core version of the LEON3 processor was implemented to demonstrate the applicability and assertiveness of the approach. Several critical application codes were compiled to this processor, which was mapped into a Xilinx Spartan 3E FPGA. Experimental results demonstrate that the proposed approach is very effective on combining system high-performance with critical task schedulability within timing deadline.