Uma metodologia para identificação de módulos de circuitos integrados propensos a erros

• Ano de defesa: 2011
• Autor(a) principal: Jose Augusto Miranda Nacif
• Tipo de documento: Tese
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Universidade Federal de Minas Gerais
• Palavras-chave em Português: Circuitos integrados Integração em escala muito ampla; Circuitos integrados; Computação; Circuitos digitais
• Link de acesso: https://hdl.handle.net/1843/SLSS-8GYG2K

Verifying large industrial designs is getting harder each day. The currentverification methodologies can not guarantee bug free designs. Considering that is not possible to check all states of complex designs, the verification team should define coverage levels for each integrated circuit module. If the coverage of errorprone modules is prioritized, it is possible to identify more bugs in less time. The novelty of this work is to propose a methodology that is able to build a model which points the hardware modules that are most likely to have undetected design bugs. The model is built using revision history information and complexitymetrics extracted from concurrent versioning systems and bug tracking systems. The proposed methodology allows the identification, for a specific project, of which metrics are correlated with bugs. Thus, we are able to allocate verificatio resources more efficiently and define high risk modules to be submitted to a more rigorous verification process.The proposed methodology is validated in an experimental environment composed by metrics, data, and tools. The studied metrics are extracted by comercial and open source tools. The data used in this work are repositories of processors described in hardware description languages. In order to automate the complexity and design history metrics extraction, two tools were developed. The first, BugReporter, is a tool used to help users to report project bugs, using keywords defined by BugLanguage. The second, EyesOn, automates the extraction, storage and visualization of complexity and history metrics. We present results from the use of the proposed methodology in two processors: MIPS and OpenSPARC. For each of these processors, linear, Poisson, negative binomial, and logistic models are built. In the MIPS processor, linear model presents the best results. In the OpenSPARC project, the best performance is reached by negative binomial model. In both cases, the best models use five metrics. We also discuss results from the use of history metrics in the MIPS processor. We propose an algorithm that uses the number of modifications to dynamically build a list of error-prone modules. During the modules development the list stores, in 80% of the time, the modules that had reported errors. Thus, the results achieved by the proposed methodology could be extended with new studies using other data sets and metrics.