Geração de código para arquiteturas reconfiguráveis

• Ano de defesa: 2019
• Autor(a) principal: Pedro Henrique Moreira Caldeira
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Minas Gerais
• Palavras-chave em Português: Computação – Teses; Arquitetura de computador – Teses; Compiladores (Programas de computador) – Teses; Linguagem de programação (Computadores) – Teses; Compiladores; FPGA; Linguages de Programação; Arquitetura de Computadores; Java; MapReduce; Performance
• Link de acesso: https://hdl.handle.net/1843/51804

Recent years have seen a surge in the popularity of Field-Programmable Gate Arrays (FPGAs). Programmers can use them to develop high-performance systems that are not only efficient in time, but also in energy. Yet, programming FPGAs remains a difficult task. Even though there exist today OpenCL interfaces to synthesize such hardware, higher-level programming languages, such as Java, C# or Python remain distant from them. In this work, we describe a compiler, and its supporting runtime environment, that reduces this distance, translating functional code written in Java to the Intel HARP platform. Thus, we bring two contributions. First, the insight that a functional-style library is a good starting point to bridge the gap between high-level programming idioms and FPGAs. Second, the implementation of this system itself, including the compiler, its intermediate representation, and all the runtime support necessary to shield developers from the task of transferring data back and forth between the host CPU and the accelerator. To demonstrate the effectiveness of our system, we have used it to implement different benchmarks, used in image processing and datamining. For large inputs, we can observe consistent 20x speedups over the Java Virtual Machine across all our benchmarks. Depending on the target function that we compile, this speedup can be as large as 280.