Static CMOS complex gates: electrical investigation of design strategies

• Ano de defesa: 2022
• Autor(a) principal: Kessler, Henrique Caldas
• Orientador(a): Porto, Marcelo Schiavon
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Pelotas
• Programa de Pós-Graduação: Programa de Pós-Graduação em Computação
• Departamento: Centro de Desenvolvimento Tecnológico
• País: Brasil
• Palavras-chave em Português: Static CMOS complex gates; Cell design automation; Transistor network; Electrical simulation; Portas complexas CMOS estáticas; Projeto automático de células lógicas; Rede de transistores; Simulação elétrica
• Área do conhecimento CNPq: CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://guaiaca.ufpel.edu.br/handle/prefix/8340

Recent developments in electronic design automation tools vastly reduce the design cost of supergates, enabling an alternative approach to logic synthesis. Despite many design strategies targeting the transistors network in supergates, their comparisons are often limited to metrics such as the number of transistors used or circuit total stack, lacking an in-depth electrical evaluation. This thesis uses an electrical characterization framework to study multiple supergate design strategies. A study on the 3982 logic functions of the 4 input P-class shows that topologies that optimize both pull-up and pull-down networks individually presented better overall electrical characteristics. The results also suggest that reducing the logic gate stack or the number of transistors does not necessarily lead to better performance. Also, a strong dependency between the effectiveness of a supergate design methodology and the logic function is found. The evaluated supergates designs did not possess a defined transistor reordering technique. In this thesis, a well-established reordering algorithm is evaluated and a proposed modification is presented. Observing supergates with different results from the baseline algorithm, the proposed algorithm produced gates with smaller power dissipation and critical delay in over 60% of the studied cases. It is also observed a lack of different transistor sizing techniques in works that use supergates. They are often limited to using minimum transistor dimensions or the Logical Effort technique. In this thesis, a methodology to adapt the Logical Effort technique for low-power applications is proposed. Results show significant improvements on up to 99.9% of the studied cases in power-performance trade-off across multiple simulation environments. Comparing supergates with technology-mapped circuits on small logic functions results shows that supergate-based designs reduce the average power dissipation in 84.4% of the studied cases. Despite the supergate design increasing in average the circuit critical delay by 5.8%, it achieves better power-delay-product in 2823 (70.9%) of the 3982 studied logic functions. The reduction of logic levels is the main factor for gains obtained with supergates due to the glitch power reduction. Applying supergates to a circuit with more than 800 logic gates, small gains in both power dissipation and critical delay can be achieved.