FPGA enabled heterogeneous system simulation for early design space exploration

• Ano de defesa: 2021
• Autor(a) principal: Betemps, Carlos Michel
• Orientador(a): Zatt, Bruno
• Tipo de documento: Tese
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Pelotas
• Programa de Pós-Graduação: Programa de Pós-Graduação em Computação
• Departamento: Centro de Desenvolvimento Tecnológico
• País: Brasil
• Palavras-chave em Português: Computação; Heterogeneous system simulator; FPGA simulation; Early design space exploration; Dynamic and partial reconfiguration; Partially reconfigurable regions; Simulador de sistemas heterogêneos; Simulação FPGA; Antecipada exploração do espaço de projeto; Reconfiguração dinâmica e parcial; Regiões parcialmente reconfiguráveis
• Área do conhecimento CNPq: CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://guaiaca.ufpel.edu.br/handle/prefix/7720

Heterogeneous systems architectures usually include processing elements such as Central Processing Units and General Purpose Graphics Processing Units, frequently enabling optimization opportunities in terms of execution time, consumed energy, resource utilization, and throughput. In turn, the heterogeneity brings a series of new design challenges when compared to homogeneous systems. An even more challenging scenario appears when such heterogeneous systems feature hardware acceleration through dynamic and partial FPGA (Field Programmable Gate Array) reconfiguration. This work presents a Modeling and Simulation infrastructure for early Design Space Exploration (DSE) of heterogeneous systems by comprising a methodology to create high-level models of the system and a simulator complying with those models. A designer can partition an FPGA into Partially Reconfigurable Regions (PRRs) that can pass through a Dynamic and Partial Reconfiguration (DPR) during runtime. Considering those aspects, the modeling methodology contains the flow and automatic hardware generation to annotate our simulation models. FEHetSS is an FPGA-Enabled Heterogeneous System Simulator aiming to provide support for decision making in early design phases. We describe FEHetSS presenting its structure, models, and simulation flow. FEHetSS considers the tasks’ latencies even those related to reconfiguration, also estimating the processing elements’ power and resource utilization. Based on case studies, we demonstrate the methodology and FEHetSS’s potentialities. First, we model heterogeneous systems and use FEHetSS as a tool to evaluate single-points in early DSE. Second, we conceive distinct hardware design (e.g., pipelining and parallelism) models for an application kernel and utilize FEHetSS as a tool to assist designers considering a holistic system perspective. Third, we restrict a couple of design spaces applying FEHetSS to perform exhaustive exploration. Last, we prepare a DSE environment integrating an optimization heuristic and FEHetSS, performing simulations based on exploration parameters. Case studies’ results and analysis demonstrate the infrastructure features in the modeling and simulation of FPGA-enabled heterogeneous systems.