Circuitos digitais e mistos CMOS com aplicação em medidor de energia

• Ano de defesa: 2017
• Autor(a) principal: Bezerra, Thiago Brito
• Tipo de documento: Tese
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal do Rio de Janeiro; Brasil; Instituto Alberto Luiz Coimbra de Pós-Graduação e Pesquisa de Engenharia; Programa de Pós-Graduação em Engenharia Elétrica; UFRJ
• Palavras-chave em Português: Circuitos digitais; Circuitos integrados; Circuitos com capacitores chaveados; CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA::CIRCUITOS ELETRICOS, MAGNETICOS E ELETRONICOS::CIRCUITOS ELETRONICOS
• Link de acesso: http://hdl.handle.net/11422/6077

The design of digital and mixed CMOS integrated circuits for energy meters is required in applications where energy measurement systems are installed with fast processing and low power consumption. The great challenge is to understand its operation and investigate topologies and/or design methodologies that allow to solve the difficulties in the design of integrated digital and mixed circuits, in order to find a good compromise between processing speed, power consumed and occupied area. In this work we present the development of new digital and mixed circuits to be used in an energy meter. The digital circuits uses a bypassing technique which avoids redundant calculations. This technique was applied in the low power multiplier, reducing its consumption by 40%. For the high-pass filter, the power consumption was reduced by 15%. And the low-pass filter had the consumption reduced by 26%. A pseudo-parallel sigma-delta modulator that was optimized at system level to attain maximum SNR using minimum capacitance values so that speed requirements of the analog blocks could be alleviated in order to reduce power consumption. The developed PSDM was verified by post-layout simulations, reaching a dynamic range of 99.8 dB for a signal bandwidth of 2 kHz, with an oversampling ratio of 128, occupying an area of 0.16 mm2 and consuming only 52.5 µW.