Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications

Detalhes bibliográficos
Ano de defesa: 2024
Autor(a) principal: Santos Júnior, Carlos Eduardo de Barros
Orientador(a): Não Informado pela instituição
Banca de defesa: Não Informado pela instituição
Tipo de documento: Tese
Tipo de acesso: Acesso aberto
Idioma: por
Instituição de defesa: Universidade Federal do Rio Grande do Norte
Brasil
UFRN
PROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA E DE COMPUTAÇÃO
Programa de Pós-Graduação: Não Informado pela instituição
Departamento: Não Informado pela instituição
País: Não Informado pela instituição
Palavras-chave em Português:
IoT
Link de acesso: https://repositorio.ufrn.br/handle/123456789/63475
Resumo: As IoT device usage continues to expand, ensuring secure, low-latency data exchange has become essential, driving research into blockchain-based solutions to meet these requirements. Addressing this demand, this thesis presents a reconfigurable hardware architecture for the SHA-256 hash algorithm, focusing on blockchain and IoT applications, utilizing Field Programmable Gate Arrays (FPGAs) as the target hardware to maximize performance and efficiency in data security processes. The proposed FPGA implementation provides adaptability across various environments, from network servers to energyconstrained IoT devices. Key innovations in this proposal include a multicore parallelism system that optimizes the use of available FPGA resources and a structured analysis of resource consumption, considering both clock frequency and throughput. Additionally, the thesis provides a power consumption analysis, comparing power efficiency across different hardware architectures. The proposed design achieved the implementation of 16 parallel cores on a Xilinx Virtex 6 xc6vlx240t-1ff1156 FPGA, reaching a maximum throughput of 1.4Gbps and dynamic power consumption of 0.452W. This performance represents up to 16x speedup over previous FPGA models and a reduction of up to 234.52x in dynamic power consumption compared to implementations from prior research. Additional comparisons were conducted with other hardware architectures, such as 8- and 16-bit microcontrollers, general-purpose processors, and GPUs. The results underscore the versatility and scalability of FPGA-based SHA-256 implementations for applications requiring high throughput and power efficiency, establishing this work as a significant contribution to information security and computational performance in IoT environments within a blockchain context.
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spelling Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applicationsSHA-256BlockchainFPGAIoTReconfigurable hardwareCNPQ::ENGENHARIAS::ENGENHARIA ELETRICAAs IoT device usage continues to expand, ensuring secure, low-latency data exchange has become essential, driving research into blockchain-based solutions to meet these requirements. Addressing this demand, this thesis presents a reconfigurable hardware architecture for the SHA-256 hash algorithm, focusing on blockchain and IoT applications, utilizing Field Programmable Gate Arrays (FPGAs) as the target hardware to maximize performance and efficiency in data security processes. The proposed FPGA implementation provides adaptability across various environments, from network servers to energyconstrained IoT devices. Key innovations in this proposal include a multicore parallelism system that optimizes the use of available FPGA resources and a structured analysis of resource consumption, considering both clock frequency and throughput. Additionally, the thesis provides a power consumption analysis, comparing power efficiency across different hardware architectures. The proposed design achieved the implementation of 16 parallel cores on a Xilinx Virtex 6 xc6vlx240t-1ff1156 FPGA, reaching a maximum throughput of 1.4Gbps and dynamic power consumption of 0.452W. This performance represents up to 16x speedup over previous FPGA models and a reduction of up to 234.52x in dynamic power consumption compared to implementations from prior research. Additional comparisons were conducted with other hardware architectures, such as 8- and 16-bit microcontrollers, general-purpose processors, and GPUs. The results underscore the versatility and scalability of FPGA-based SHA-256 implementations for applications requiring high throughput and power efficiency, establishing this work as a significant contribution to information security and computational performance in IoT environments within a blockchain context.À medida que o uso de dispositivos IoT continua a crescer, garantir uma troca de dados segura e de baixa latência tornou-se uma necessidade essencial, impulsionando pesquisas em soluções baseadas em blockchain para atender a esses requisitos. Em resposta a essa demanda, esta tese apresenta uma arquitetura de hardware reconfigurável para o algoritmo de hash SHA-256, com foco em aplicações de blockchain e IoT, utilizando FPGAs (Field Programmable Gate Arrays) como hardware alvo para maximizar o desempenho e a eficiência em processos de segurança de dados. A implementação proposta em FPGA oferece adaptabilidade para diferentes ambientes, desde servidores de rede até dispositivos IoT com restrições de energia. As principais inovações desta proposta incluem um sistema de paralelismo multinúcleo que otimiza o uso dos elementos disponíveis na FPGA e uma análise estruturada do consumo desses recursos, considerando tanto a frequência de clock quanto o throughput. Adicionalmente, a tese contempla uma análise de consumo de energia, comparando o desempenho de consumo de potência entre diferentes arquiteturas de hardware. O design proposto alcançou a implementação de 16 núcleos paralelos em um FPGA Xilinx Virtex 6 xc6vlx240t-1ff1156, atingindo um throughput máximo de 1,4Gbps e consumo de potência dinâmica de 0,452W. Este desempenho representa um speedUp de até 16x em relação a modelos FPGA anteriores e uma redução de até 234,52x no consumo de potência dinâmica quando comparado a implementação de pesquisas anteriores. Comparações adicionais foram realizadas com outras arquiteturas de hardware, como microcontroladores de 8 e 16 bits, processadores de uso geral e GPUs. Os resultados evidenciam a versatilidade e escalabilidade da implementação do SHA-256 em FPGA para aplicações que exigem alto throughput e eficiência no consumo de potência, posicionando este trabalho como uma contribuição significativa à segurança da informação e desempenho computacional em ambientes de IoT no contexto de blockchain.Universidade Federal do Rio Grande do NorteBrasilUFRNPROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA E DE COMPUTAÇÃOFernandes, Marcelo Augusto Costahttp://lattes.cnpq.br/1334493042199015https://orcid.org/0000-0001-7536-2506http://lattes.cnpq.br/3475337353676349Silva, Sérgio NatanDias, Leonardo AlvesSilva, Lucileide Medeiros Dantas daCoutinho, Maria Gracielly FernandesSantos Júnior, Carlos Eduardo de Barros2025-04-15T20:24:56Z2025-04-15T20:24:56Z2024-12-11info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/doctoralThesisapplication/pdfSANTOS JÚNIOR, Carlos Eduardo de Barros. Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications. Orientador: Dr. Marcelo Augusto Costa Fernandes. 2024. 100f. Tese (Doutorado em Engenharia Elétrica e de Computação) - Centro de Tecnologia, Universidade Federal do Rio Grande do Norte, Natal, 2024.https://repositorio.ufrn.br/handle/123456789/63475info:eu-repo/semantics/openAccessporreponame:Repositório Institucional da UFRNinstname:Universidade Federal do Rio Grande do Norte (UFRN)instacron:UFRN2025-04-15T20:25:30Zoai:repositorio.ufrn.br:123456789/63475Repositório InstitucionalPUBhttp://repositorio.ufrn.br/oai/repositorio@bczm.ufrn.bropendoar:2025-04-15T20:25:30Repositório Institucional da UFRN - Universidade Federal do Rio Grande do Norte (UFRN)false
dc.title.none.fl_str_mv Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications
title Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications
spellingShingle Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications
Santos Júnior, Carlos Eduardo de Barros
SHA-256
Blockchain
FPGA
IoT
Reconfigurable hardware
CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA
title_short Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications
title_full Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications
title_fullStr Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications
title_full_unstemmed Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications
title_sort Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications
author Santos Júnior, Carlos Eduardo de Barros
author_facet Santos Júnior, Carlos Eduardo de Barros
author_role author
dc.contributor.none.fl_str_mv Fernandes, Marcelo Augusto Costa
http://lattes.cnpq.br/1334493042199015
https://orcid.org/0000-0001-7536-2506
http://lattes.cnpq.br/3475337353676349
Silva, Sérgio Natan
Dias, Leonardo Alves
Silva, Lucileide Medeiros Dantas da
Coutinho, Maria Gracielly Fernandes
dc.contributor.author.fl_str_mv Santos Júnior, Carlos Eduardo de Barros
dc.subject.por.fl_str_mv SHA-256
Blockchain
FPGA
IoT
Reconfigurable hardware
CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA
topic SHA-256
Blockchain
FPGA
IoT
Reconfigurable hardware
CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA
description As IoT device usage continues to expand, ensuring secure, low-latency data exchange has become essential, driving research into blockchain-based solutions to meet these requirements. Addressing this demand, this thesis presents a reconfigurable hardware architecture for the SHA-256 hash algorithm, focusing on blockchain and IoT applications, utilizing Field Programmable Gate Arrays (FPGAs) as the target hardware to maximize performance and efficiency in data security processes. The proposed FPGA implementation provides adaptability across various environments, from network servers to energyconstrained IoT devices. Key innovations in this proposal include a multicore parallelism system that optimizes the use of available FPGA resources and a structured analysis of resource consumption, considering both clock frequency and throughput. Additionally, the thesis provides a power consumption analysis, comparing power efficiency across different hardware architectures. The proposed design achieved the implementation of 16 parallel cores on a Xilinx Virtex 6 xc6vlx240t-1ff1156 FPGA, reaching a maximum throughput of 1.4Gbps and dynamic power consumption of 0.452W. This performance represents up to 16x speedup over previous FPGA models and a reduction of up to 234.52x in dynamic power consumption compared to implementations from prior research. Additional comparisons were conducted with other hardware architectures, such as 8- and 16-bit microcontrollers, general-purpose processors, and GPUs. The results underscore the versatility and scalability of FPGA-based SHA-256 implementations for applications requiring high throughput and power efficiency, establishing this work as a significant contribution to information security and computational performance in IoT environments within a blockchain context.
publishDate 2024
dc.date.none.fl_str_mv 2024-12-11
2025-04-15T20:24:56Z
2025-04-15T20:24:56Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/doctoralThesis
format doctoralThesis
status_str publishedVersion
dc.identifier.uri.fl_str_mv SANTOS JÚNIOR, Carlos Eduardo de Barros. Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications. Orientador: Dr. Marcelo Augusto Costa Fernandes. 2024. 100f. Tese (Doutorado em Engenharia Elétrica e de Computação) - Centro de Tecnologia, Universidade Federal do Rio Grande do Norte, Natal, 2024.
https://repositorio.ufrn.br/handle/123456789/63475
identifier_str_mv SANTOS JÚNIOR, Carlos Eduardo de Barros. Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications. Orientador: Dr. Marcelo Augusto Costa Fernandes. 2024. 100f. Tese (Doutorado em Engenharia Elétrica e de Computação) - Centro de Tecnologia, Universidade Federal do Rio Grande do Norte, Natal, 2024.
url https://repositorio.ufrn.br/handle/123456789/63475
dc.language.iso.fl_str_mv por
language por
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universidade Federal do Rio Grande do Norte
Brasil
UFRN
PROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA E DE COMPUTAÇÃO
publisher.none.fl_str_mv Universidade Federal do Rio Grande do Norte
Brasil
UFRN
PROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA E DE COMPUTAÇÃO
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