Um framework para geração automática de sistemas multiprocessados reconfiguráveis heterogêneos

• Ano de defesa: 2017
• Autor(a) principal: Sfreddo, Josimar
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• dARK ID: ark:/26339/00130000180m6
• Idioma: por
• Instituição de defesa: Universidade Federal de Santa Maria; Brasil; Ciência da Computação; UFSM; Programa de Pós-Graduação em Ciência da Computação; Centro de Tecnologia
• Palavras-chave em Português: Sistemas embarcados; Arquiteturas reconfiguráveis; Exploração de ILP; Exploração de área; Redução de área; Embedded systems; Reconfigurable architectures; ILP exploitation; Area exploitation; Area reduction; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://repositorio.ufsm.br/handle/1/15441

Nowadays, embedded systems are getting more complex since functionalities are converging to a single device, thus demanding for more processing capability. However, modeling embedded processors is not a trivial task because they execute applications that have different behaviors, some applications benefit more from ILP exploitation and other TLP. There are still those applications where both can bring great benefits in reducing the execution time. Therefore it is essential to analyze application behavior to define which form of parallelism is the most suitable to be explored. Further, a multiprocessor system with reconfigurable architecture contributes greatly to increase the performance of embedded applications. However, an inadequate modeling of the reconfigurable system can result in a huge area design. This work proposes a framework that automatically models a reconfigurable multiprocessor system with heterogeneous organization considering the behavior of applications. The goal is to compose a multiprocessor system that provides the correct processing capability in terms of ILP and therefore provides an ideal chip area in the execution of applications. The results demonstrate that the framework reduced, on average, by 75.86% chip area without losses in performance.