Uma heurística polinomial para escalonamento de loops em arquiteturas reconfiguráveis de grão grosso

• Ano de defesa: 2013
• Autor(a) principal: Lopes, Vinícius Duarte
• Orientador(a): Ferreira, Ricardo dos Santos
• Banca de defesa: Goulart, Carlos de Castro , Nacif, José Augusto Miranda
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Viçosa
• Programa de Pós-Graduação: Mestrado em Ciência da Computação
• Departamento: Metodologias e técnicas da Computação; Sistemas de Computação
• País: BR
• Palavras-chave em Português: Hardware reconfigurável; Módulo sheduling; Arquiteturas reconfiguráveis
• Palavras-chave em Inglês: Reconfigurable hardware; Module sheduling; Reconfigurable Architectures
• Área do conhecimento CNPq: CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://locus.ufv.br/handle/123456789/2654

Nowadays reconfigurable architectures are attractive both in performance and low power consumption for applications with computing intensive loops. FPGAs are fine-grained architectures that offer the possibility of acceleration for these applications, however, the mapping process is typically time consuming and complex. Although Coarse Grained Reconfigurable Architectures (CGRAs) provide less flexibility than FPGAs, they has less complex mapping. The goal of this work is the runtime mapping of the dataflow graph, which represents a loop, on a reconfigurable architecture. The problem is NP-Complete and the heuristics found in the literature are not feasible for a dynamic implementation. We propose a heuristic solution that utilizes two distinct mechanisms: an architecture that simplifies the most of the mapping process, with minimal degradation in performance, and an algorithm to perform the mapping at run-time application. While previous solutions require seconds to mapping applications, the proposed solution requires only microseconds to generate near-optimal mappings. Accordingly, the presented solution enables the use of the Just-In-Time compilation, which can be used in dynamic contexts where various applications share a reconfigurable architecture with a possibility of change in composition of processing elements or scenarios with presence of hardware failures. Furthermore, we present an implementation model of the algorithm in hardware, which aims to be 90% faster when compared to the software Just-In-Time solution.