Algoritmo modular de estimação de sincrofasores de sequência positiva

• Ano de defesa: 2020
• Autor(a) principal: Carvalho, Gabriel Ubirajara de
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Tecnológica Federal do Paraná; Pato Branco; Brasil; Programa de Pós-Graduação em Engenharia Elétrica; UTFPR
• Palavras-chave em Português: Redes elétricas inteligentes; Sistemas de Energia Elétrica; Algoritmos computacionais; Smart power grids; Electric power systems; Computer algorithms; CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA; Engenharia/Tecnologia/Gestão
• Link de acesso: http://repositorio.utfpr.edu.br/jspui/handle/1/5077

The trend of increasing the insertion of distributed generation sources to the electrical system, together with technological advances in the area of data processing and communication, has fostered the discussion on smart grids. In this context, the synchronized Phasor Measurement Unit (PMU) presents itself as a fundamental element to supply the necessary data on different points of the system, both in terms of transmission and distribution. Although the implementation of Synchronized Phasor Measurement Systems (SPMS) is of great interest to operators, budgetary barriers prevent their dissemination on a large scale. Therefore, research is aimed at proposing the construction of a low-cost PMU. Most of the proposals use algorithms based on the Discrete Fourier Transform (DFT) for synchrophasors estimation, a technique used since the first symmetric component distance relay produced in the 1980s, which served as a basis to give rise to PMU at the end of same decade. DFT requires little computational effort, and that was what motivated its use at that time due to the scarce processing resources. However, this technique has its limitations. Currently, the abundance of computational resources allows the study and implementation of more robust and less limited routines, capable of improving the features and functionality of the devices. The present work presents the design, analysis and experimental test of a positive sequence synchrophasor measurement algorithm based on a Synchronous Reference Frame Phase-locked Loop (SRF-PLL) in accordance with IEEE C37.118.1-2011 standards and its amendment C37.118.1a-2014. The approach presented consists of a three-stage algorithm, the first being a three-phase demodulation, which separates the positive sequence component from the negative sequence component in the frequency domain, as well as removes the zero sequence. The second stage is a Finite Impulse Response (FIR) filter that is applied in order to improve noise rejection and interference. This class of digital filters was chosen for its characteristic of linear phase and constant group delay. Finally, the last stage is performed by an SRF-PLL with magnitude normalization and proportional-integral controller, which estimates amplitude, phase, frequency and Rate Of Change Of Frequency (ROCOF). The experimental results obtained by a testing platform shows that the steady state criteria are met, with emphasis on immunity against out-of-band interference.