Implementação em FPGA de compensadores de desvios para conversor analógico digital intercalado

• Ano de defesa: 2016
• Autor(a) principal: Hofmann, Maicon Bruno
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Tecnológica Federal do Paraná; Curitiba; Brasil; Programa de Pós-Graduação em Engenharia Elétrica e Informática Industrial; UTFPR
• Palavras-chave em Português: Conversores analógicos-digitais; Arranjos de lógica programável em campo; VHDL (Linguagem descritiva de hardware); Engenharia elétrica; Analog-to-digital converters; Field programmable gate arrays; VHDL (Computer hardware description language); Electric engineering; CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA::CIRCUITOS ELETRICOS, MAGNETICOS E ELETRONICOS::CIRCUITOS ELETRONICOS
• Link de acesso: http://repositorio.utfpr.edu.br/jspui/handle/1/1809

This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.