Estudo e implementação de sistemas de localização em hardware de lógica programável para utilização em rede de sensores sem fio

• Ano de defesa: 2013
• Autor(a) principal: Shirai, Alysson Hikaru
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Tecnológica Federal do Paraná; Curitiba; Programa de Pós-Graduação em Engenharia Elétrica e Informática Industrial
• Palavras-chave em Português: Algorítmos; Sistemas de comunicação sem fio; Arranjos de lógica programável em campo; Métodos de simulação; Algorithms; Wireless communication systems; Field programmable gate arrays; Simulation methods
• Link de acesso: http://repositorio.utfpr.edu.br/jspui/handle/1/511

Wireless sensor networks (WSN) have been the central theme of many researches in actuality. In certain applications, like, for example, the ones that need to know from where the data is being sent or in cases which the sensor node need to know its own position to perform some action, location mechanism is indispensable. However, the execution of these algorithms is costly for the sensor nodes. Concomitantly, the advent of low power FPGAs made feasible the application of programmable devices in WSNs and applications involving dynamic reconfiguration of FPGA in sensor nodes increased the use of these devices in WSNs. Joining these demands, the goal of this master thesis is to study and implement locating systems in programmable logic hardware, aiming at meeting applications in WSN. Employing a dedicated hardware block in sensor node to compute the position minimizes its CPU usage, and this hardware can even be just a part of a larger system implemented in FPGA. The localization process is based on the use of distances, measured between the sensor node with unknown position and the reference nodes, determined from RSSI measurements, and the use of specific algorithms that calculate the desired position. The main steps were: review of the literature, modeling the behavior of the RSSI measurements, performance analysis of the algorithms and hardware design. Through the performed simulations it was possible to develop methodologies and tools to generate optimized locating hardware. The development of this work allowed to evaluate the feasibility of the floating point and fixed point, to set the appropriate architecture for the hardware and to find the proper dimension of the number of bits required in the implementations.