Pulsar : towards a synthesis flow for QDI circuits

• Ano de defesa: 2019
• Autor(a) principal: Sartori, Marcos Luiggi Lemos
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul; Escola Politécnica; Brasil; PUCRS; Programa de Pós-Graduação em Ciência da Computação
• Palavras-chave em Português: Asynchronous Circuits; QDI; EDA; NCL; Modelling; Synthesis; Design; Circuitos Assíncronos; Modelagem; Síntese; Projeto; CIENCIA DA COMPUTACAO::TEORIA DA COMPUTACAO
• Link de acesso: http://tede2.pucrs.br/tede2/handle/tede/9814

Asynchronous quasi-delay-insensitive (QDI) circuits are known for their robustness against PVT variations. This makes them good candidates for enabling aggressive voltage scaling design techniques. However, the adoption of QDI design by industries is hindered by: (i) the dependency on specialised design tools for QDI circuits; (ii) the lack of integration with traditional ASIC design flows. This Dissertation presents Pulsar, a new synthesis flow for QDI circuit design. Pulsar leverages commercial EDA tools for design capture, dual-rail expansion, technology mapping and optimisation of QDI circuits. Commercial EDA tools enable designers to define performance targets and naturally balance power and area optimisation. The Dissertation brings six main original contributions: (i) an extended pseudosynchronous flow, with new register models; (ii) a generalised SDDS-NCL flow to deal with both combinational and sequential circuits; (iii) the proposition of half-buffer channel network (HBCN), a new model for timing analysis of half-buffer asynchronous circuits; (iv) a linear programming formulation to constrain a design to a target asynchronous cycle time. (v) an RTL-like design capture technique and an associated dual-rail expansion technique; (vi) a tool that automatically extracts the HBCN model of a circuit and computes its synthesis constraints. Results show that Pulsar enables the design of asynchronous circuits from an RTL-like description under cycle-time constraints. Pulsar enables the sign-off of target cycle times for QDI circuits using commercial EDA tools. This is a breakthrough for QDI designers, as they can now safely bound worst case performance metrics for applications. Moreover, Pulsar enables designers to naturally trade performance for power or area optimisations, whenever there is slack in timing budgets.