Curbing the design complexity of asynchronous circuits

• Ano de defesa: 2023
• Autor(a) principal: Sartori, Marcos Luiggi Lemos
• Tipo de documento: Tese
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul; Escola Politécnica; Brasil; PUCRS; Programa de Pós-Graduação em Ciência da Computação
• Palavras-chave em Português: Asynchronous Circuits; ST; QDI; Electronic design automation; Circuitos Assíncronos; Automação de projeto eletrônico; CIENCIA DA COMPUTACAO::TEORIA DA COMPUTACAO
• Link de acesso: https://tede2.pucrs.br/tede2/handle/tede/11634

The design of self-timed (ST) asynchronous circuits offers robustness to delay variations but faces challenges that require innovative solutions. This Thesis comprehensively enhances Pulsar, a previous contribution of the Author, focused on designing asynchronous circuits with the help of commercial electronic design automation tools. Pulsar originally targeted the pseudo-synchronous spatially distributed dual spacer null convention logic (PSSDDS-NCL) ST template. The Thesis introduces two new asynchronous ST templates and extends Pulsar to support these.The first is the weakly-indicating dual spacer (WInDS), a weakly-indicating enhancement to PS-SDDS-NCL. The second is the asynchronous limited hysteresis organisation (ALHO) ST template, which employs non-hysteretic gates. These are proposed and integrated within the Pulsar framework. They address some challenges in ST circuit implementation, reflecting the Thesis motivation to overcome hurdles in designing asynchronous circuits whilst tackling area, power and performance overheads. This Thesis also extends Pulsar to support choice, offering more design flexibility. It demonstrates the use of Pulsar to design simple circuits and a fully functional RISC-V processor architecture implementation with the introduced templates. Additional contributions include the formalisation of requirements to build functional ST circuits, providing foundational principles for their effective design and implementation. This formalisation enabled the construction of more relaxed ST circuits compared to the conservative quasi-delay-insensitive (QDI) paradigm. The need to differentiate QDI and more relaxed ST circuits in terms of timing assumptions resulted in the proposal of a classification system for asynchronous circuits. These contributions collectively provide a new structured approach to asynchronous circuit design, culminating in the non-hysteretic ALHO ST template and the extensions of Pulsar. The work lays a foundation for the continued exploration, research, and development in the field of asynchronous circuit design, building on the capabilities of Pulsar and offering new insights into the design process of ST circuits.