Acceleration of AEAD algorithms for resource-constrained embedded devices

• Ano de defesa: 2024
• Autor(a) principal: Moura, Nicolas Silva
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul; Escola Politécnica; Brasil; PUCRS; Programa de Pós-Graduação em Ciência da Computação
• Palavras-chave em Português: Lightweight Cryptography; Ascon; RISC-V; Hardware Acceleration; Criptografia Leve; Aceleração de Hardware; CIENCIA DA COMPUTACAO::TEORIA DA COMPUTACAO
• Link de acesso: https://tede2.pucrs.br/tede2/handle/tede/11645

The amount of sensitive information and data processed on IoT devices constantly increases. As a result, security has become a crucial concern. Although data encryption is necessary, the large overheads that encryption algorithms typically require to protect data are rarely tolerable on low-end devices. This has led to the emergence of a new branch of research called Lightweight Cryptography (LWC), which aims to introduce new algorithms that provide acceptable levels of security while consuming as few resources as possible. Due to the growing relevance of this field and the many divergent proposals, the National Institute of Standards and Technology (NIST) launched a competition to select an LWC algorithm to standardize similarly to that previously done for the Advanced Encryption Standard (AES). In February 2023, the Ascon algorithm was announced as the competition winner, and it is expected to be standardized by NIST in 2024. This work presents a comparative evaluation between three authenticated encryption algorithms with associated data (AEAD), namely, Ascon, AES-128 in CCM mode, and ChaCha20-Poly1305 in the context of a low-complexity RISC-V processor, considering the algorithm executing in software and with instruction set extensions (ISEs), comparing their performance and trade-offs in a 28nm FDSOI technology from ST Microelectronics. The results present a comprehensive evaluation of PPA (Power, Performance and Area) for the three AEAD algorithms, showing a performance gain of 95.1%, 60.3%, and 5.2%, along with an increase in energy efficiency of 94.2%, 65.6%, and 17.2%, for AES, Ascon, and ChaCha20-Poly1305, respectively. The area overheads were observed to be up to 9%. Such results demonstrate that devices with limited resources that encrypt a high message volume benefit significantly from hardware acceleration.