Error Correction Codes Based on Region Selection Codes

• Ano de defesa: 2023
• Autor(a) principal: Silva, Felipe Gaspar Alan e
• Orientador(a): Silveira, Jarbas Aryel Nunes da
• Tipo de documento: Tese
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Área do conhecimento CNPq: CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA
• Link de acesso: http://repositorio.ufc.br/handle/riufc/76792

The continuous decrease in the scale of transistors spurred the advent of System-on-Chips (SoCs), allowing the insertion of more computational logic in an integrated circuit (IC), increasing its processing capacity and functionalities. However, this process made electronic devices more susceptible to external effects, mainly radiation. Among modern ICs, memory circuits (e.g., SRAM and DRAM) are very susceptible to radiation effects, and may present different types of failures, with multiple-bit inversion (MBUs) and stored information corruption being the most recurrent types. In this context, Error Correction Codes (ECCs) have been widely used to increase the reliability of data stored in memory. ECCs with linear and matrix format excel in two-dimensional memories. Linear format codes have one dimension and are used to protect a dataset in this single dimension. Array format codes are two-dimensional, protecting an array of data. This thesis had the goal of developing a set of ECCs based on Region Selection Code (RSC), which consists of separating memory data into regions, and through logical operations and simple steps to perform MBU corrections. The first ECC developed was the Matrix Region Selection Code (MRSC), a matrix format code that was developed for adjacent error correction, managing to correct 100% of 2-bit errors. Two other extension approaches were developed: Extended Matrix Region Selection Code (eMRSC) and Triple Burst Error Corrector - Region Selection Code (TBEC-RSC). eMRSC is also an extension of the matrix format, but with two configurations: one with greater error correction capability and another with a smaller number of redundancy bits. TBEC-RSC is a proposed extension to linear format, able to correct up to 3-bit burst errors. All proposals were compared with other works in the area considering correction capacity, reliability and synthesis cost. Finally, the results collected from experiments showed that ECCs based on RSC logic showed excellent error correction capability and good reliability rates (e.g., TBEC-RSC corrected approximately 40% of 8-bit burst errors), also characterized by low synthesis cost (e.g., MRSC consumed 91.2% less power than the Reed-Muller code), which made them have the best ratio of correction coverage per synthesis cost among the compared ECCs.