Projeto de um conversor analógico-digital por aproximação sucessiva com regime monotônico de chaveamento capacitivo.

• Ano de defesa: 2019
• Autor(a) principal: COSTA FILHO, Antonio Agripino da.
• Orientador(a): LIMA, Antonio Marcus Nogueira. , MORAIS, Marcos Ricardo De Alcantara.
• Banca de defesa: NETO, José Sérgio da Rocha. , MELCHER, Elmar Uwe Kurt.
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Campina Grande
• Programa de Pós-Graduação: PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA
• Departamento: Centro de Engenharia Elétrica e Informática - CEEI
• País: Brasil
• Palavras-chave em Português: Conversor Analógico-Digital; Chaveamento Monotônico; Modo Assíncrono; Microeletrônica; Analog-Digital Converter; Monotonic Switching; Asynchronous Mode; Microelectronics
• Área do conhecimento CNPq: Engenharia Elétrica
• Link de acesso: https://dspace.sti.ufcg.edu.br/handle/riufcg/26802

In this work, an analog-digital converter based on the successive approximation technique and a monotonic capacitive switching regime was designed. The analog-digital converter is designed to operate in asynchronous mode and use a double-tail dynamic comparator. A 180 nm process design kit (PDK) and an analog electronic circuit design automatic tool were used. The project flow included the following steps: circuit design, component sizing, steady state and dynamic simulations (schematic and layout level), as well as functionality and performance evaluations. A reference voltage circuit based on the beta multiplier voltage reference topology has been designed for use with the analog-digital converter. From this reference voltage circuit was obtained 1.2 V, exhibiting a 1 kHz power supply rejection rate of -54.47 dB and a temperature coefficient of 23.99 ppm/°C in the range of -40 °C at 175 °C; these values were obtained from layout level simulations. The converter was developed at the schematic level, using a double-tail dynamic comparator with PMOS inputs, metalisolator-metal capacitors (5.36 fF unit capacitors - minimum available value at PDK) and the bootstrap topology for the drive input circuit. The analog-digital converter is powered by 1.8 V, operates at a conversion rate of 30 MHz, converts input differential signals (≤ 3.4 V) with 10 bit encoded resolution in excess-K and has an average consumption of 1.14 mW in converting a 14.74 MHz input signal; these values were obtained from schematic level simulations. The results presented corroborate the correctness of the project flow used, as well as the feasibility of the projected analog-digital converter, in terms of resolution (10 bits), conversion rate (30 MHz) and average consumption (1.14 mW).