Implementação de redes neurais por pulsos a partir de sinapses memristivas

Detalhes bibliográficos
Ano de defesa: 2022
Autor(a) principal: Wellington de Oliveira Avelino
Orientador(a): Não Informado pela instituição
Banca de defesa: Não Informado pela instituição
Tipo de documento: Tese
Tipo de acesso: Acesso aberto
Idioma: por
Instituição de defesa: Universidade Federal de Minas Gerais
Programa de Pós-Graduação: Não Informado pela instituição
Departamento: Não Informado pela instituição
País: Não Informado pela instituição
Palavras-chave em Português:
Link de acesso: https://hdl.handle.net/1843/52456
Resumo: Artificial intelligence (AI) applications are increasingly present and necessary, especially neural networks (NN). The limited scalability of CMOS (complementary metal-oxide-semiconductor) technology and the increasing computational complexity of these applications require more energy efficiency and scalable hardware implementations. The main computational primitives of NNs are multiply-and-accumulate operations that lead to a significant data movement between memory and processing unit on von Neumann-based computational architectures. A promising alternative is the mimicry of event-based computing, as in neuromorphic systems, co-locating memory and processing. New neurologic-inspired circuit elements represent a new alternative to achieve the much-desired computational efficiency of the brain, among them, a series of nanoscale devices, known as memristors, were proposed to be used as fundamental elements in the creation of artificial synapses and neurons. In this scenario, the efforts of this work aim to boost the implementation of memristor-based spiking neural networks (SNN) to technological maturity. This thesis focuses on constructive aspects of networks, highlighting methodologies for network element coupling, establishing satisfactory conditions to maximize efficiency in information processing and implementation of local training techniques. For this purpose, a testing platform and a graphical user interface environment were specially developed for a demonstration of a fully hardware neural network based on memristive synapses, neuron circuits from NDR devices (negative differential resistance) and complementary circuits. In addition, prototypical experiments were demonstrated to validate inference and learning in neural networks from these components.
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spelling 2023-04-25T17:13:18Z2025-09-09T01:20:36Z2023-04-25T17:13:18Z2022-05-20https://hdl.handle.net/1843/52456Artificial intelligence (AI) applications are increasingly present and necessary, especially neural networks (NN). The limited scalability of CMOS (complementary metal-oxide-semiconductor) technology and the increasing computational complexity of these applications require more energy efficiency and scalable hardware implementations. The main computational primitives of NNs are multiply-and-accumulate operations that lead to a significant data movement between memory and processing unit on von Neumann-based computational architectures. A promising alternative is the mimicry of event-based computing, as in neuromorphic systems, co-locating memory and processing. New neurologic-inspired circuit elements represent a new alternative to achieve the much-desired computational efficiency of the brain, among them, a series of nanoscale devices, known as memristors, were proposed to be used as fundamental elements in the creation of artificial synapses and neurons. In this scenario, the efforts of this work aim to boost the implementation of memristor-based spiking neural networks (SNN) to technological maturity. This thesis focuses on constructive aspects of networks, highlighting methodologies for network element coupling, establishing satisfactory conditions to maximize efficiency in information processing and implementation of local training techniques. For this purpose, a testing platform and a graphical user interface environment were specially developed for a demonstration of a fully hardware neural network based on memristive synapses, neuron circuits from NDR devices (negative differential resistance) and complementary circuits. In addition, prototypical experiments were demonstrated to validate inference and learning in neural networks from these components.porUniversidade Federal de Minas GeraisInteligência artificialSistemas neuromórficosMemristoresRedes neurais por pulsosTreinamento localTransportadores de corrente de segunda geraçãoEngenharia elétricaInteligência artificialRedes neurais (Computação)Implementação de redes neurais por pulsos a partir de sinapses memristivasSpiking neural network implementation from memristive synapsesinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/doctoralThesisWellington de Oliveira Avelinoinfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFMGinstname:Universidade Federal de Minas Gerais (UFMG)instacron:UFMGhttp://lattes.cnpq.br/5714230080065380Gilberto Medeiros Ribeirohttp://lattes.cnpq.br/1681880375960859Janaina Goncalves GuimarãesJosé Alexandre DinizJhonattan Córdoba RamírezWagner Nunes RodriguesAs aplicações de inteligência artificial (IA) estão cada vez mais presentes e necessárias, principalmente as redes neurais (RN). A limitação no escalonamento da tecnologia CMOS (do inglês complementary metal-oxide-semiconductor) e a crescente complexidade computacional dessas aplicações exigem implementações de hardware mais energeticamente eficientes e escaláveis. As principais primitivas de computação de RNs são operações de multiplicações e acumulações que levam a um movimento significativo de dados entre memória e unidade de processamento nos sistemas computacionais baseados na arquitetura de von Neumann. Uma alternativa promissora é a mimetização da computação baseada em eventos, como em sistemas neuromórficos, colocalizando memória e processamento. Novos elementos de circuito inspirados no funcionamento neurológico representam uma nova alternativa para atingir a tão desejada eficiência computacional do cérebro, entre eles, uma série de dispositivos nanoescalares, conhecidos como memristores, foram propostos para serem usados como elementos fundamentais na construção de sinapses e neurônios artificiais. Nesse cenário, os esforços desse trabalho visam impulsionar a implementação de redes neurais por pulsos (RNP) com memristores à maturidade tecnológica. Essa tese foca em aspectos construtivos das redes, destacando metodologias para o acoplamento entre os elementos da rede estabelecendo condições satisfatórias para maximizar a eficiência no processamento da informação e implementação de técnicas de treinamento locais. Com esse propósito, uma plataforma de testes e um ambiente gráfico de interface com o usuário foram especialmente desenvolvidos e participaram na demonstração de uma rede neural inteiramente implementada em hardware a partir de sinapses memristivas, circuitos de neurônios a partir de dispositivos de NDR (do inglês negative differential resistance) e circuitos complementares. Ainda, experimentos prototípicos foram demonstrados para validar inferência e aprendizagem em redes neurais a partir desses componentes.https://orcid.org/0000-0002-9273-9827BrasilENG - DEPARTAMENTO DE ENGENHARIA ELÉTRICAPrograma de Pós-Graduação em Engenharia ElétricaUFMGLICENSElicense.txttext/plain2118https://repositorio.ufmg.br//bitstreams/43924e3b-ce86-4057-98e3-7e9551a08db2/downloadcda590c95a0b51b4d15f60c9642ca272MD51falseAnonymousREADORIGINAL6.1 Tese - Wellington de Oliveira Avelino - PDFA.pdfapplication/pdf7274471https://repositorio.ufmg.br//bitstreams/4bb32f83-6593-46fc-a801-69de3bcaadc1/downloada177dcdf3a71ae81f376155d22974d58MD52trueAnonymousREAD1843/524562025-09-08 22:20:36.736open.accessoai:repositorio.ufmg.br:1843/52456https://repositorio.ufmg.br/Repositório InstitucionalPUBhttps://repositorio.ufmg.br/oairepositorio@ufmg.bropendoar:2025-09-09T01:20:36Repositório Institucional da UFMG - Universidade Federal de Minas Gerais (UFMG)falseTElDRU7Dh0EgREUgRElTVFJJQlVJw4fDg08gTsODTy1FWENMVVNJVkEgRE8gUkVQT1NJVMOTUklPIElOU1RJVFVDSU9OQUwgREEgVUZNRwoKQ29tIGEgYXByZXNlbnRhw6fDo28gZGVzdGEgbGljZW7Dp2EsIHZvY8OqIChvIGF1dG9yIChlcykgb3UgbyB0aXR1bGFyIGRvcyBkaXJlaXRvcyBkZSBhdXRvcikgY29uY2VkZSBhbyBSZXBvc2l0w7NyaW8gSW5zdGl0dWNpb25hbCBkYSBVRk1HIChSSS1VRk1HKSBvIGRpcmVpdG8gbsOjbyBleGNsdXNpdm8gZSBpcnJldm9nw6F2ZWwgZGUgcmVwcm9kdXppciBlL291IGRpc3RyaWJ1aXIgYSBzdWEgcHVibGljYcOnw6NvIChpbmNsdWluZG8gbyByZXN1bW8pIHBvciB0b2RvIG8gbXVuZG8gbm8gZm9ybWF0byBpbXByZXNzbyBlIGVsZXRyw7RuaWNvIGUgZW0gcXVhbHF1ZXIgbWVpbywgaW5jbHVpbmRvIG9zIGZvcm1hdG9zIMOhdWRpbyBvdSB2w61kZW8uCgpWb2PDqiBkZWNsYXJhIHF1ZSBjb25oZWNlIGEgcG9sw610aWNhIGRlIGNvcHlyaWdodCBkYSBlZGl0b3JhIGRvIHNldSBkb2N1bWVudG8gZSBxdWUgY29uaGVjZSBlIGFjZWl0YSBhcyBEaXJldHJpemVzIGRvIFJJLVVGTUcuCgpWb2PDqiBjb25jb3JkYSBxdWUgbyBSZXBvc2l0w7NyaW8gSW5zdGl0dWNpb25hbCBkYSBVRk1HIHBvZGUsIHNlbSBhbHRlcmFyIG8gY29udGXDumRvLCB0cmFuc3BvciBhIHN1YSBwdWJsaWNhw6fDo28gcGFyYSBxdWFscXVlciBtZWlvIG91IGZvcm1hdG8gcGFyYSBmaW5zIGRlIHByZXNlcnZhw6fDo28uCgpWb2PDqiB0YW1iw6ltIGNvbmNvcmRhIHF1ZSBvIFJlcG9zaXTDs3JpbyBJbnN0aXR1Y2lvbmFsIGRhIFVGTUcgcG9kZSBtYW50ZXIgbWFpcyBkZSB1bWEgY8OzcGlhIGRlIHN1YSBwdWJsaWNhw6fDo28gcGFyYSBmaW5zIGRlIHNlZ3VyYW7Dp2EsIGJhY2stdXAgZSBwcmVzZXJ2YcOnw6NvLgoKVm9jw6ogZGVjbGFyYSBxdWUgYSBzdWEgcHVibGljYcOnw6NvIMOpIG9yaWdpbmFsIGUgcXVlIHZvY8OqIHRlbSBvIHBvZGVyIGRlIGNvbmNlZGVyIG9zIGRpcmVpdG9zIGNvbnRpZG9zIG5lc3RhIGxpY2Vuw6dhLiBWb2PDqiB0YW1iw6ltIGRlY2xhcmEgcXVlIG8gZGVww7NzaXRvIGRlIHN1YSBwdWJsaWNhw6fDo28gbsOjbywgcXVlIHNlamEgZGUgc2V1IGNvbmhlY2ltZW50bywgaW5mcmluZ2UgZGlyZWl0b3MgYXV0b3JhaXMgZGUgbmluZ3XDqW0uCgpDYXNvIGEgc3VhIHB1YmxpY2HDp8OjbyBjb250ZW5oYSBtYXRlcmlhbCBxdWUgdm9jw6ogbsOjbyBwb3NzdWkgYSB0aXR1bGFyaWRhZGUgZG9zIGRpcmVpdG9zIGF1dG9yYWlzLCB2b2PDqiBkZWNsYXJhIHF1ZSBvYnRldmUgYSBwZXJtaXNzw6NvIGlycmVzdHJpdGEgZG8gZGV0ZW50b3IgZG9zIGRpcmVpdG9zIGF1dG9yYWlzIHBhcmEgY29uY2VkZXIgYW8gUmVwb3NpdMOzcmlvIEluc3RpdHVjaW9uYWwgZGEgVUZNRyBvcyBkaXJlaXRvcyBhcHJlc2VudGFkb3MgbmVzdGEgbGljZW7Dp2EsIGUgcXVlIGVzc2UgbWF0ZXJpYWwgZGUgcHJvcHJpZWRhZGUgZGUgdGVyY2Vpcm9zIGVzdMOhIGNsYXJhbWVudGUgaWRlbnRpZmljYWRvIGUgcmVjb25oZWNpZG8gbm8gdGV4dG8gb3Ugbm8gY29udGXDumRvIGRhIHB1YmxpY2HDp8OjbyBvcmEgZGVwb3NpdGFkYS4KCkNBU08gQSBQVUJMSUNBw4fDg08gT1JBIERFUE9TSVRBREEgVEVOSEEgU0lETyBSRVNVTFRBRE8gREUgVU0gUEFUUk9Dw41OSU8gT1UgQVBPSU8gREUgVU1BIEFHw4pOQ0lBIERFIEZPTUVOVE8gT1UgT1VUUk8gT1JHQU5JU01PLCBWT0PDiiBERUNMQVJBIFFVRSBSRVNQRUlUT1UgVE9ET1MgRSBRVUFJU1FVRVIgRElSRUlUT1MgREUgUkVWSVPDg08gQ09NTyBUQU1Cw4lNIEFTIERFTUFJUyBPQlJJR0HDh8OVRVMgRVhJR0lEQVMgUE9SIENPTlRSQVRPIE9VIEFDT1JETy4KCk8gUmVwb3NpdMOzcmlvIEluc3RpdHVjaW9uYWwgZGEgVUZNRyBzZSBjb21wcm9tZXRlIGEgaWRlbnRpZmljYXIgY2xhcmFtZW50ZSBvIHNldSBub21lKHMpIG91IG8ocykgbm9tZXMocykgZG8ocykgZGV0ZW50b3IoZXMpIGRvcyBkaXJlaXRvcyBhdXRvcmFpcyBkYSBwdWJsaWNhw6fDo28sIGUgbsOjbyBmYXLDoSBxdWFscXVlciBhbHRlcmHDp8OjbywgYWzDqW0gZGFxdWVsYXMgY29uY2VkaWRhcyBwb3IgZXN0YSBsaWNlbsOnYS4K
dc.title.none.fl_str_mv Implementação de redes neurais por pulsos a partir de sinapses memristivas
dc.title.alternative.none.fl_str_mv Spiking neural network implementation from memristive synapses
title Implementação de redes neurais por pulsos a partir de sinapses memristivas
spellingShingle Implementação de redes neurais por pulsos a partir de sinapses memristivas
Wellington de Oliveira Avelino
Engenharia elétrica
Inteligência artificial
Redes neurais (Computação)
Inteligência artificial
Sistemas neuromórficos
Memristores
Redes neurais por pulsos
Treinamento local
Transportadores de corrente de segunda geração
title_short Implementação de redes neurais por pulsos a partir de sinapses memristivas
title_full Implementação de redes neurais por pulsos a partir de sinapses memristivas
title_fullStr Implementação de redes neurais por pulsos a partir de sinapses memristivas
title_full_unstemmed Implementação de redes neurais por pulsos a partir de sinapses memristivas
title_sort Implementação de redes neurais por pulsos a partir de sinapses memristivas
author Wellington de Oliveira Avelino
author_facet Wellington de Oliveira Avelino
author_role author
dc.contributor.author.fl_str_mv Wellington de Oliveira Avelino
dc.subject.por.fl_str_mv Engenharia elétrica
Inteligência artificial
Redes neurais (Computação)
topic Engenharia elétrica
Inteligência artificial
Redes neurais (Computação)
Inteligência artificial
Sistemas neuromórficos
Memristores
Redes neurais por pulsos
Treinamento local
Transportadores de corrente de segunda geração
dc.subject.other.none.fl_str_mv Inteligência artificial
Sistemas neuromórficos
Memristores
Redes neurais por pulsos
Treinamento local
Transportadores de corrente de segunda geração
description Artificial intelligence (AI) applications are increasingly present and necessary, especially neural networks (NN). The limited scalability of CMOS (complementary metal-oxide-semiconductor) technology and the increasing computational complexity of these applications require more energy efficiency and scalable hardware implementations. The main computational primitives of NNs are multiply-and-accumulate operations that lead to a significant data movement between memory and processing unit on von Neumann-based computational architectures. A promising alternative is the mimicry of event-based computing, as in neuromorphic systems, co-locating memory and processing. New neurologic-inspired circuit elements represent a new alternative to achieve the much-desired computational efficiency of the brain, among them, a series of nanoscale devices, known as memristors, were proposed to be used as fundamental elements in the creation of artificial synapses and neurons. In this scenario, the efforts of this work aim to boost the implementation of memristor-based spiking neural networks (SNN) to technological maturity. This thesis focuses on constructive aspects of networks, highlighting methodologies for network element coupling, establishing satisfactory conditions to maximize efficiency in information processing and implementation of local training techniques. For this purpose, a testing platform and a graphical user interface environment were specially developed for a demonstration of a fully hardware neural network based on memristive synapses, neuron circuits from NDR devices (negative differential resistance) and complementary circuits. In addition, prototypical experiments were demonstrated to validate inference and learning in neural networks from these components.
publishDate 2022
dc.date.issued.fl_str_mv 2022-05-20
dc.date.accessioned.fl_str_mv 2023-04-25T17:13:18Z
2025-09-09T01:20:36Z
dc.date.available.fl_str_mv 2023-04-25T17:13:18Z
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dc.identifier.uri.fl_str_mv https://hdl.handle.net/1843/52456
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dc.publisher.none.fl_str_mv Universidade Federal de Minas Gerais
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