Implementação de redes neurais por pulsos a partir de sinapses memristivas

• Ano de defesa: 2022
• Autor(a) principal: Wellington de Oliveira Avelino
• Tipo de documento: Tese
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Minas Gerais
• Palavras-chave em Português: Engenharia elétrica; Inteligência artificial; Redes neurais (Computação); Sistemas neuromórficos; Memristores; Redes neurais por pulsos; Treinamento local; Transportadores de corrente de segunda geração
• Link de acesso: https://hdl.handle.net/1843/52456

Artificial intelligence (AI) applications are increasingly present and necessary, especially neural networks (NN). The limited scalability of CMOS (complementary metal-oxide-semiconductor) technology and the increasing computational complexity of these applications require more energy efficiency and scalable hardware implementations. The main computational primitives of NNs are multiply-and-accumulate operations that lead to a significant data movement between memory and processing unit on von Neumann-based computational architectures. A promising alternative is the mimicry of event-based computing, as in neuromorphic systems, co-locating memory and processing. New neurologic-inspired circuit elements represent a new alternative to achieve the much-desired computational efficiency of the brain, among them, a series of nanoscale devices, known as memristors, were proposed to be used as fundamental elements in the creation of artificial synapses and neurons. In this scenario, the efforts of this work aim to boost the implementation of memristor-based spiking neural networks (SNN) to technological maturity. This thesis focuses on constructive aspects of networks, highlighting methodologies for network element coupling, establishing satisfactory conditions to maximize efficiency in information processing and implementation of local training techniques. For this purpose, a testing platform and a graphical user interface environment were specially developed for a demonstration of a fully hardware neural network based on memristive synapses, neuron circuits from NDR devices (negative differential resistance) and complementary circuits. In addition, prototypical experiments were demonstrated to validate inference and learning in neural networks from these components.