Cell implementation through boolean satisfiability for conventional and emerging technologies

• Ano de defesa: 2022
• Autor(a) principal: Cardoso, Maicon Schneider
• Orientador(a): Marques, Felipe de Souza
• Tipo de documento: Tese
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Pelotas
• Programa de Pós-Graduação: Programa de Pós-Graduação em Computação
• Departamento: Centro de Desenvolvimento Tecnológico
• País: Brasil
• Palavras-chave em Português: Computação; Electronic design automation; Cell implementation; Boolean satisfiability; Static CMOS complex gate; Quantum-dot cellular automata; Nanomagnetic logic; Ferramenta de apoio ao projeto eletrônico; Projeto físico de células lógicas; Satisfatibilidade booleana
• Área do conhecimento CNPq: CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://guaiaca.ufpel.edu.br/handle/prefix/8444

The electronic design automation (EDA) tools take a crucial role in the modern digital circuits and systems synthesis, where the design challenges are not only numerous but also complex. In this scenario, the Boolean satisfiability (SAT) solvers have been employed lately as a useful engine for computing the solutions on these EDA tools, producing circuits with good quality in a reasonable computing time. On a similar note, the versatility provided by the satisfiability paradigm can be explored for different design purposes ranging from conventional to emerging technologies. Thus, in this thesis, we employ this approach to generate area-optimized circuits in three different technologies: static CMOS complex gates (SCCG), quantum-dot cellular automata (QCA), and nanomagnetic logic (NML). Considering this, the proposed methods were able to encode all the design constraints into a discrete constraint model, using satisfiability solvers as the core of the optimization task. Regarding the SCCG synthesis, the experiments have shown that, besides providing improvements on layout area, the solutions produced using the proposed method also presented optimization in other geometrical parameters such as in wirelength and number of contacts when compared to a traditional meta-heuristic approach. Furthermore, following the experiments on the emerging technologies, the QCA and NML synthesis methodologies were able to provide solutions with less area when compared to other graph-based techniques available in the literature for most of the assessed cases. Moreover, the latency of these solutions also presented an optimization, thus providing a wide design exploration scenario where it is possible to choose whether to use smaller or faster circuits depending on the specifications.