Uma arquitetura reconfigurável para processamento in situ utilizando redes neurais sem pesos

• Ano de defesa: 2018
• Autor(a) principal: Ferreira, Victor da Cruz
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal do Rio de Janeiro; Brasil; Instituto Alberto Luiz Coimbra de Pós-Graduação e Pesquisa de Engenharia; Programa de Pós-Graduação em Engenharia de Sistemas e Computação; UFRJ
• Palavras-chave em Português: FPGA; in-situ; Dataflow; CNPQ::ENGENHARIAS
• Link de acesso: http://hdl.handle.net/11422/13077

A couple years ago, limitations in power and transistor area began to charge the integrated circuit industry into a new frontier that involved heterogeneous computer architectures and energy-efficient designs. Now-a-days, Field Programmable Gate Arrays (FPGAs) play an important role on these systems due to their high flexibility and energy-efficient processing capabilities. However, due to the increasing number of accelerators and new devices embedded with parallel capabilities there is an increase in data movement through the network. This increase in traffic may result in overall system performance depreciation. One way to decrease the data movement is to process the data in-situ, which means processing the data near it’s location. With this concept in mind, this work aims at designing and evaluating a smart disk system for in-situ face recognition through a Weightless artificial Neural Network (WNN) co-processor designed in High-Level Synthesis (HLS) and implemented in the system’s FPGA. Preliminaries results in performance, circuit-area and energy consumption results shows that the co-processor can efficiently learn and recognize faces faster than the system’s embedded ARM processor, while also significantly reducing network traffic.