Projeto de moduladores sigma-delta de alta resolução e largura de banda em tecnologia BCD de 130 nm

• Ano de defesa: 2024
• Autor(a) principal: Oliveira, Renan Dotto Pacheco de
• Orientador(a): Aguirre, Paulo César Comassetto de
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal do Pampa
• Programa de Pós-Graduação: Mestrado Acadêmico em Engenharia Elétrica
• Departamento: Campus Alegrete
• País: Brasil
• Palavras-chave em Português: Modulador Sigma-Delta; Conversores Analógico-Digitais; Projeto Analógico; Sigma-Delta Modulator; Analog-to-Digital Converters; Analog Design
• Área do conhecimento CNPq: ENGENHARIAS

The goal of this work is to analyze and describe the design methodology of high-resolution, wide-bandwidth continuous-time sigma-delta modulators in 130 nm BCD technology. The design methodology at high-level is carried out in the Matlab/Simulink environment, which allows for the optimization and validation of the modulator using ideal models. Subsequently, electrical-level modeling is carried out using Verilog-A blocks, and finally, implementation at the transistor level. In this work, the Cascade of Integrators in Feedforward (CIFF) topology was chosen, and the designed modulator is of the fourth order. The design was conducted using a supply voltage of 5 V, a signal bandwidth of 125 kHz, and a sampling frequency of 32 MHz. Schematic-level simulations indicate an SNDR of 96.93 dB considering noise, and a total power dissipation of 19.87 mW, resulting in a Figure of Merit (FoM) of 171.1 dB. This parameter is a metric that helps evaluate the system’s efficiency, considering energy consumption and performance. The modulator achieved an effective number of bits (ENOB) of 15.81 bits, which is limited by thermal noise. The performance is comparable to the state-of-the-art, despite the designed modulator is powered by a 5-V power supply. Subsequently, a software was developed in Python to assist in the calculation of passive components of continuous-time sigma-delta modulators of third and fourth order using the CIFF topology. Finally, this work explores the use of resonators with a single operational transconductance amplifier within the loop filter to reduce the number of integrators and power dissipation. Keywords: Sigma-Delta Modulator, Analog-to-Digital Converters, Analog Design.