Asynchronous circuits : innovations in components, cell libraries and design templates
Ano de defesa: | 2016 |
---|---|
Autor(a) principal: | |
Orientador(a): | |
Banca de defesa: | |
Tipo de documento: | Tese |
Tipo de acesso: | Acesso aberto |
Idioma: | eng |
Instituição de defesa: |
Pontif?cia Universidade Cat?lica do Rio Grande do Sul
|
Programa de Pós-Graduação: |
Programa de P?s-Gradua??o em Ci?ncia da Computa??o
|
Departamento: |
Faculdade de Inform?tica
|
País: |
Brasil
|
Palavras-chave em Português: | |
Área do conhecimento CNPq: | |
Link de acesso: | http://tede2.pucrs.br/tede2/handle/tede/6635 |
Resumo: | For decades now, the synchronous paradigm has been the major choice of the industry for building integrated circuits. Unfortunately, with the development of semiconductor industry, power budgets got tighter and delay uncertainties increased, making synchronous design a complex task. Some of the reasons behind that are the increase in process variability, the losses in wire performance and the uncertainties in the operating condition of devices. These and other factors significantly impact transistor electrical characteristics, making it more complicated to meet timing closure in synchronous systems and compromising power efficiency. The asynchronous paradigm emerges as an efficient alternative to current design approaches, given its inherent high robustness against delay variations and suitability to low-power and high-performance design. However, while a major segment of the design automation industry was developed to support synchronous design, currently, design automation for asynchronous circuits is limited, to say the least. Furthermore, basic components for semi-custom design approaches, typically available in standard cell libraries were optimized to target synchronous implementations and those necessary to support asynchronous design were also left behind. This Thesis proposes new techniques to optimize asynchronous design, from cell to system level. We start by analyzing and optimizing basic components for asynchronous design and then propose new manners of implementing them at the transistor level. The proposed optimizations and novel components allow better exploring power, delay and area trade-offs, providing a guideline for asynchronous designers. We then explore how to design these components as cells for building a library to support semi-custom design. To that extent, we propose a completely automated flow for designing such libraries. This flow comprises transistors sizing and electrical characterization tools, developed in this Thesis, and a layout generation tool, developed by a fellow research group. We also provide a freely available library, designed with the flow, with hundreds of components that were extensively validated with post-layout simulations. Using this library we devised new templates for designing asynchronous circuits at the system level, exploring an automated synthesis solution and expanding design space exploration. Compared to a similar state-of-the-art solution, our latest template provides almost twice better energy efficiency and comprises an original automated method for technology mapping and synthesis optimizations. The contributions of this Thesis allowed the construction of an infrastructure for building asynchronous designs, paving the way to explore their usage to solve contemporary and future challenges in integrated circuit design. |
id |
P_RS_b5d3a1aa29460e805e570fcd91a585e8 |
---|---|
oai_identifier_str |
oai:tede2.pucrs.br:tede/6635 |
network_acronym_str |
P_RS |
network_name_str |
Biblioteca Digital de Teses e Dissertações da PUC_RS |
repository_id_str |
|
spelling |
Calazans, Ney Laert Vilar265.426.840-34http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4781414E5Beerel, Peter A.632.090.390-20http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4475704Y0Moreira, Matheus Trevisan2016-05-03T16:50:54Z2016-01-14http://tede2.pucrs.br/tede2/handle/tede/6635For decades now, the synchronous paradigm has been the major choice of the industry for building integrated circuits. Unfortunately, with the development of semiconductor industry, power budgets got tighter and delay uncertainties increased, making synchronous design a complex task. Some of the reasons behind that are the increase in process variability, the losses in wire performance and the uncertainties in the operating condition of devices. These and other factors significantly impact transistor electrical characteristics, making it more complicated to meet timing closure in synchronous systems and compromising power efficiency. The asynchronous paradigm emerges as an efficient alternative to current design approaches, given its inherent high robustness against delay variations and suitability to low-power and high-performance design. However, while a major segment of the design automation industry was developed to support synchronous design, currently, design automation for asynchronous circuits is limited, to say the least. Furthermore, basic components for semi-custom design approaches, typically available in standard cell libraries were optimized to target synchronous implementations and those necessary to support asynchronous design were also left behind. This Thesis proposes new techniques to optimize asynchronous design, from cell to system level. We start by analyzing and optimizing basic components for asynchronous design and then propose new manners of implementing them at the transistor level. The proposed optimizations and novel components allow better exploring power, delay and area trade-offs, providing a guideline for asynchronous designers. We then explore how to design these components as cells for building a library to support semi-custom design. To that extent, we propose a completely automated flow for designing such libraries. This flow comprises transistors sizing and electrical characterization tools, developed in this Thesis, and a layout generation tool, developed by a fellow research group. We also provide a freely available library, designed with the flow, with hundreds of components that were extensively validated with post-layout simulations. Using this library we devised new templates for designing asynchronous circuits at the system level, exploring an automated synthesis solution and expanding design space exploration. Compared to a similar state-of-the-art solution, our latest template provides almost twice better energy efficiency and comprises an original automated method for technology mapping and synthesis optimizations. The contributions of this Thesis allowed the construction of an infrastructure for building asynchronous designs, paving the way to explore their usage to solve contemporary and future challenges in integrated circuit design.O paradigma s?ncrono foi, por d?cadas, a principal escolha da ind?stria para o projeto de circuitos integrados. Infelizmente, com o desenvolvimento da ind?stria de semicondutores, restri??es de projeto relativas ? pot?ncia de um circuito e incertezas de atrasos aumentaram, dificultando o projeto s?ncrono. Alguns dos motivos para isso s?o o aumento na variabilidade dos processos de fabrica??o de dispositivo, as perdas de desempenho relativas em fios e as incertezas temporais causadas por variabilidades nas condi??es operacionais de dispositivos. Dessa forma, o paradigma ass?ncrono surge como uma alternativa, devido ? sua robustez contra varia??es temporais e suporte ao projeto de circuitos de alto desepenho e baixo consumo. Entretanto, grande parte da ind?stria de ferramentas de automa??o de projeto eletr?nico foi desenvolvida visando o projeto de circuitos s?ncronos e atualmente o suporte a circuitos ass?ncronos ? consideravelmente limitado. Esta Tese prop?e novas t?cnicas de projeto para otimizar circuitos ass?ncronos, desde o n?vel de c?lulas ao n?vel de sistema. Come?amos analisando e otimizando componentes b?sicos para o projeto desses circuitos e depois apresentamos novas solu??es para implement?-los no n?vel de transistores. As otimiza??es propostas permitem uma melhor explora??o dos par?metros desses circuitos, incluindo pot?ncia, atraso e ?rea. Em um segundo momento, exploramos o uso desses componentes como c?lulas para a gera??o de uma biblioteca de suporte ao projeto semi-dedicado de circuitos ass?ncronos. Nesse contexto, propomos um fluxo completamente automatizado para projetar tais bibliotecas. O fluxo compreende ferramentas de dimensionamento de transistores e caracteriza??o el?trica, desenvolvidas nesta Tese, e uma ferramenta de projeto de leiaute, desenvolvida por um grupo de pesquisa parceiro. Esse trabalho tamb?m apresenta uma biblioteca aberta, com centenas de componentes validados extensivamente atrav?s de simula??es p?s-leiaute. Al?m disso, usando essa biblioteca desenvolvemos novos templates para o projeto de circuitos ass?ncronos no n?vel de sistema, propondo um fluxo autom?tico para s?ntese e mapeamento tecnol?gico. Comparado a uma solu??o ass?ncrona no estado da arte, nosso mais novo template apresenta uma efici?ncia energ?tica quase duas vezes maior. As contribui??es desta Tese permitiram a constru??o de uma infraestrutura para o projeto de circuitos ass?ncronos, abrindo caminho para a explora??o do uso de templates ass?ncronos para solucionar problemas modernos e futuros no projeto de circuitos integrados.Submitted by Setor de Tratamento da Informa??o - BC/PUCRS (tede2@pucrs.br) on 2016-05-03T16:50:54Z No. of bitstreams: 1 TES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf: 12630678 bytes, checksum: 24f95d03626ea6a376f29220bb4e1177 (MD5)Made available in DSpace on 2016-05-03T16:50:54Z (GMT). No. of bitstreams: 1 TES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf: 12630678 bytes, checksum: 24f95d03626ea6a376f29220bb4e1177 (MD5) Previous issue date: 2016-01-14Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior - CAPESConselho Nacional de Pesquisa e Desenvolvimento Cient?fico e Tecnol?gico - CNPqFunda??o de Amparo ? Pesquisa do Estado do Rio Grande do Sul - FAPERGSapplication/pdfhttp://tede2.pucrs.br:80/tede2/retrieve/164669/TES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf.jpgengPontif?cia Universidade Cat?lica do Rio Grande do SulPrograma de P?s-Gradua??o em Ci?ncia da Computa??oPUCRSBrasilFaculdade de Inform?ticaCIRCUITOS ASS?NCRONOSPROJETO DE CIRCUITOSARQUITETURA DE REDESENGENHARIA EL?TRICAINFORM?TICACIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAOAsynchronous circuits : innovations in components, cell libraries and design templatesCircuitos ass?ncronos : inova??es em componentes, bibliotecas de c?lulas e templates de projetoinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/doctoralThesis1974996533081274470600600600600600600-300854251040114914436717112058112045092075167498588264571-2555911436985713659-3614735573891122254info:eu-repo/semantics/openAccessreponame:Biblioteca Digital de Teses e Dissertações da PUC_RSinstname:Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)instacron:PUC_RSTHUMBNAILTES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf.jpgTES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf.jpgimage/jpeg4165http://tede2.pucrs.br/tede2/bitstream/tede/6635/4/TES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf.jpga1162145c06705939c5c78aae039e5aeMD54TEXTTES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf.txtTES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf.txttext/plain620157http://tede2.pucrs.br/tede2/bitstream/tede/6635/3/TES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf.txtdc43cfe74892510d5411085cb6ae4c50MD53ORIGINALTES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdfTES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdfapplication/pdf12630678http://tede2.pucrs.br/tede2/bitstream/tede/6635/2/TES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf24f95d03626ea6a376f29220bb4e1177MD52LICENSElicense.txtlicense.txttext/plain; charset=utf-8610http://tede2.pucrs.br/tede2/bitstream/tede/6635/1/license.txt5a9d6006225b368ef605ba16b4f6d1beMD51tede/66352016-05-03 20:00:41.77oai:tede2.pucrs.br:tede/6635QXV0b3JpemHDp8OjbyBwYXJhIFB1YmxpY2HDp8OjbyBFbGV0csO0bmljYTogQ29tIGJhc2Ugbm8gZGlzcG9zdG8gbmEgTGVpIEZlZGVyYWwgbsK6OS42MTAsIGRlIDE5IGRlIGZldmVyZWlybyBkZSAxOTk4LCBvIGF1dG9yIEFVVE9SSVpBIGEgcHVibGljYcOnw6NvIGVsZXRyw7RuaWNhIGRhIHByZXNlbnRlIG9icmEgbm8gYWNlcnZvIGRhIEJpYmxpb3RlY2EgRGlnaXRhbCBkYSBQb250aWbDrWNpYSBVbml2ZXJzaWRhZGUgQ2F0w7NsaWNhIGRvIFJpbyBHcmFuZGUgZG8gU3VsLCBzZWRpYWRhIGEgQXYuIElwaXJhbmdhIDY2ODEsIFBvcnRvIEFsZWdyZSwgUmlvIEdyYW5kZSBkbyBTdWwsIGNvbSByZWdpc3RybyBkZSBDTlBKIDg4NjMwNDEzMDAwMi04MSBiZW0gY29tbyBlbSBvdXRyYXMgYmlibGlvdGVjYXMgZGlnaXRhaXMsIG5hY2lvbmFpcyBlIGludGVybmFjaW9uYWlzLCBjb25zw7NyY2lvcyBlIHJlZGVzIMOgcyBxdWFpcyBhIGJpYmxpb3RlY2EgZGEgUFVDUlMgcG9zc2EgYSB2aXIgcGFydGljaXBhciwgc2VtIMO0bnVzIGFsdXNpdm8gYW9zIGRpcmVpdG9zIGF1dG9yYWlzLCBhIHTDrXR1bG8gZGUgZGl2dWxnYcOnw6NvIGRhIHByb2R1w6fDo28gY2llbnTDrWZpY2EuCg==Biblioteca Digital de Teses e Dissertaçõeshttp://tede2.pucrs.br/tede2/PRIhttps://tede2.pucrs.br/oai/requestbiblioteca.central@pucrs.br||opendoar:2016-05-03T23:00:41Biblioteca Digital de Teses e Dissertações da PUC_RS - Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)false |
dc.title.por.fl_str_mv |
Asynchronous circuits : innovations in components, cell libraries and design templates |
dc.title.alternative.por.fl_str_mv |
Circuitos ass?ncronos : inova??es em componentes, bibliotecas de c?lulas e templates de projeto |
title |
Asynchronous circuits : innovations in components, cell libraries and design templates |
spellingShingle |
Asynchronous circuits : innovations in components, cell libraries and design templates Moreira, Matheus Trevisan CIRCUITOS ASS?NCRONOS PROJETO DE CIRCUITOS ARQUITETURA DE REDES ENGENHARIA EL?TRICA INFORM?TICA CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
title_short |
Asynchronous circuits : innovations in components, cell libraries and design templates |
title_full |
Asynchronous circuits : innovations in components, cell libraries and design templates |
title_fullStr |
Asynchronous circuits : innovations in components, cell libraries and design templates |
title_full_unstemmed |
Asynchronous circuits : innovations in components, cell libraries and design templates |
title_sort |
Asynchronous circuits : innovations in components, cell libraries and design templates |
author |
Moreira, Matheus Trevisan |
author_facet |
Moreira, Matheus Trevisan |
author_role |
author |
dc.contributor.advisor1.fl_str_mv |
Calazans, Ney Laert Vilar |
dc.contributor.advisor1ID.fl_str_mv |
265.426.840-34 |
dc.contributor.advisor1Lattes.fl_str_mv |
http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4781414E5 |
dc.contributor.advisor-co1.fl_str_mv |
Beerel, Peter A. |
dc.contributor.authorID.fl_str_mv |
632.090.390-20 |
dc.contributor.authorLattes.fl_str_mv |
http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4475704Y0 |
dc.contributor.author.fl_str_mv |
Moreira, Matheus Trevisan |
contributor_str_mv |
Calazans, Ney Laert Vilar Beerel, Peter A. |
dc.subject.por.fl_str_mv |
CIRCUITOS ASS?NCRONOS PROJETO DE CIRCUITOS ARQUITETURA DE REDES ENGENHARIA EL?TRICA INFORM?TICA |
topic |
CIRCUITOS ASS?NCRONOS PROJETO DE CIRCUITOS ARQUITETURA DE REDES ENGENHARIA EL?TRICA INFORM?TICA CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
dc.subject.cnpq.fl_str_mv |
CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO |
description |
For decades now, the synchronous paradigm has been the major choice of the industry for building integrated circuits. Unfortunately, with the development of semiconductor industry, power budgets got tighter and delay uncertainties increased, making synchronous design a complex task. Some of the reasons behind that are the increase in process variability, the losses in wire performance and the uncertainties in the operating condition of devices. These and other factors significantly impact transistor electrical characteristics, making it more complicated to meet timing closure in synchronous systems and compromising power efficiency. The asynchronous paradigm emerges as an efficient alternative to current design approaches, given its inherent high robustness against delay variations and suitability to low-power and high-performance design. However, while a major segment of the design automation industry was developed to support synchronous design, currently, design automation for asynchronous circuits is limited, to say the least. Furthermore, basic components for semi-custom design approaches, typically available in standard cell libraries were optimized to target synchronous implementations and those necessary to support asynchronous design were also left behind. This Thesis proposes new techniques to optimize asynchronous design, from cell to system level. We start by analyzing and optimizing basic components for asynchronous design and then propose new manners of implementing them at the transistor level. The proposed optimizations and novel components allow better exploring power, delay and area trade-offs, providing a guideline for asynchronous designers. We then explore how to design these components as cells for building a library to support semi-custom design. To that extent, we propose a completely automated flow for designing such libraries. This flow comprises transistors sizing and electrical characterization tools, developed in this Thesis, and a layout generation tool, developed by a fellow research group. We also provide a freely available library, designed with the flow, with hundreds of components that were extensively validated with post-layout simulations. Using this library we devised new templates for designing asynchronous circuits at the system level, exploring an automated synthesis solution and expanding design space exploration. Compared to a similar state-of-the-art solution, our latest template provides almost twice better energy efficiency and comprises an original automated method for technology mapping and synthesis optimizations. The contributions of this Thesis allowed the construction of an infrastructure for building asynchronous designs, paving the way to explore their usage to solve contemporary and future challenges in integrated circuit design. |
publishDate |
2016 |
dc.date.accessioned.fl_str_mv |
2016-05-03T16:50:54Z |
dc.date.issued.fl_str_mv |
2016-01-14 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/doctoralThesis |
format |
doctoralThesis |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://tede2.pucrs.br/tede2/handle/tede/6635 |
url |
http://tede2.pucrs.br/tede2/handle/tede/6635 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.program.fl_str_mv |
1974996533081274470 |
dc.relation.confidence.fl_str_mv |
600 600 600 600 600 600 |
dc.relation.department.fl_str_mv |
-3008542510401149144 |
dc.relation.cnpq.fl_str_mv |
3671711205811204509 |
dc.relation.sponsorship.fl_str_mv |
2075167498588264571 -2555911436985713659 -3614735573891122254 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
application/pdf |
dc.publisher.none.fl_str_mv |
Pontif?cia Universidade Cat?lica do Rio Grande do Sul |
dc.publisher.program.fl_str_mv |
Programa de P?s-Gradua??o em Ci?ncia da Computa??o |
dc.publisher.initials.fl_str_mv |
PUCRS |
dc.publisher.country.fl_str_mv |
Brasil |
dc.publisher.department.fl_str_mv |
Faculdade de Inform?tica |
publisher.none.fl_str_mv |
Pontif?cia Universidade Cat?lica do Rio Grande do Sul |
dc.source.none.fl_str_mv |
reponame:Biblioteca Digital de Teses e Dissertações da PUC_RS instname:Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS) instacron:PUC_RS |
instname_str |
Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS) |
instacron_str |
PUC_RS |
institution |
PUC_RS |
reponame_str |
Biblioteca Digital de Teses e Dissertações da PUC_RS |
collection |
Biblioteca Digital de Teses e Dissertações da PUC_RS |
bitstream.url.fl_str_mv |
http://tede2.pucrs.br/tede2/bitstream/tede/6635/4/TES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf.jpg http://tede2.pucrs.br/tede2/bitstream/tede/6635/3/TES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf.txt http://tede2.pucrs.br/tede2/bitstream/tede/6635/2/TES_MATHEUS_TREVISAN_MOREIRA_COMPLETO.pdf http://tede2.pucrs.br/tede2/bitstream/tede/6635/1/license.txt |
bitstream.checksum.fl_str_mv |
a1162145c06705939c5c78aae039e5ae dc43cfe74892510d5411085cb6ae4c50 24f95d03626ea6a376f29220bb4e1177 5a9d6006225b368ef605ba16b4f6d1be |
bitstream.checksumAlgorithm.fl_str_mv |
MD5 MD5 MD5 MD5 |
repository.name.fl_str_mv |
Biblioteca Digital de Teses e Dissertações da PUC_RS - Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS) |
repository.mail.fl_str_mv |
biblioteca.central@pucrs.br|| |
_version_ |
1796793219194814464 |